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I2C_read
说明: I2C读程序,通过状态机描叙,仿真达到要求(I2C Reading, depicts through the state machine, called Simulation)
- 2006-04-07 15:51:19下载
- 积分:1
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一个同步有限状态机(FSM)的设计是一个数字的共同任务…
Designing a synchronous finite state machine (FSM) is a common task for a digital
logic engineer. This paper discusses a variety of issues regarding FSM design using
Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
different methodologies are compared using real-world examples.
- 2022-01-26 02:12:10下载
- 积分:1
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ALU指令
alu 模块,算术逻辑单元,实现简单的控制模块,有最基本的几条指令-alu instruction
- 2022-09-28 07:05:02下载
- 积分:1
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encode
(7 4)汉明编码源程序,简单实用,可供大家下载,如有问题,望大家多多包含!((74) Hamming code source, simple and practical, available for everyone to download and, if problems, hope you lot included!)
- 2010-01-13 11:37:25下载
- 积分:1
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自己编的一个分频器的程序模版 虽然原理很简单,经过多次实践很实用 被多次用在其它的程序中...
自己编的一个分频器的程序模版 虽然原理很简单,经过多次实践很实用 被多次用在其它的程序中-own series of the dividers of a procedure template Although very simple principle, after repeated practice by many very practical use in other proceedings, and,
- 2022-02-15 15:20:10下载
- 积分:1
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PL_2FSK
基于VHDl的2FSK调制!用的是altera的quartus11软件(Based on VHDl the 2FSK modulation)
- 2012-12-13 17:20:54下载
- 积分:1
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verilog时钟分频器~ 50hmz波特率9600bps,使用~
verilog分频器~时钟为50hmz,波特率采用9600bps~-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~
- 2022-06-03 13:21:28下载
- 积分:1
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hls_bluebook
非常好的catapult学习书, catabult 可用于高级综合,由c产生vhdl/verilog(very nice book for catabult study)
- 2011-08-18 16:15:08下载
- 积分:1
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BmpDecoder
适用于Altera FPGA Nios II平台uClinux OpenCV之BmpDecoder的源码(Souce code of BmpDecoder for Altera FPGA Nios II uClinux OpenCV)
- 2011-02-11 16:43:45下载
- 积分:1
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verilog_lab_solution
Verilog 实验代码。。。经典的,里面都是完整的项目文件。 ISE环境。(Verilog test code. . . Classic, which is a complete project file. ISE environment.)
- 2011-12-01 23:44:40下载
- 积分:1