8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。-8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission.
FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.
利用VHDL实现CPLD（EPM240T100C5）的串口发送程序-Using VHDL realize CPLD (EPM240T100C5) Serial sending procedures
用AHDL语言编写,MAXPULS开发.通信不受外部时钟速率和数据字节数目限制.-with AHDL prepared MAXPULS development. Communications from external clock rate and restriction on the number of data bytes.
基于FPGA的7x7块交织器设计，程序分交织、解交织两部分，并在QUARTUS II 9.0 下仿真通过，内附模块详细端口说明及仿真分析文件。
LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现-LDPC code of the message node (Bitnode) news update process of the VHDL language
这是一个HDB3编码器，可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列-This is a HDB3 encoder, can be transformed into an ordinary binary sequences in order to comply with the rules of HDB3 bipolar coding sequence
altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II
this come from alter ,you can look and find it on line.
USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code
合众大公司XILINX_V4实验箱原理图-United XILINX_V4 large companies schematic experimental box
buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键-buffer_display is 4X4KEYPAD output module. It showed six consecutive Press
基于FPGA的快速傅立叶变换实现，适合fpga工程技术人员参考设计-FPGA-based Fast Fourier Transform for fpga reference design engineers
I2C总线在可编程逻辑器件上实现的VHDL源码-VHDL source codes for realizing I2C
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