登录
首页 » VHDL » buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键...

buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键...

于 2022-12-12 发布 文件大小:161.38 kB
0 101
下载积分: 2 下载次数: 1

代码说明:

buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键-buffer_display is 4X4KEYPAD output module. It showed six consecutive Press

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论


0 个回复

  • uart
    uart发射机Verilog HDL代码(Verilog HDL code uart transmitter)
    2011-05-21 21:37:01下载
    积分:1
  • leadingzero
    使用并行结构对32位数据进行前导零检测,使用Verilog编程(Use parallel structure to the 32-bit data, leading zero detection, using Verilog Programming)
    2010-05-12 10:48:36下载
    积分:1
  • alpha-beta
    阿尔法贝塔滤波器,是卡曼滤波器的简化,比卡曼滤波器速度快。这是一个实例。(aplha-beta filter is filter that faster than kalman filter)
    2020-11-25 20:09:31下载
    积分:1
  • ModelSim-gaojishiyong--Camp
    FPGA开发仿真工具modelsim的高级进阶教程,包括如何写脚本文件和后台批处理文件(FPGA Development Advanced simulation tools modelsim tutorial, including how to write a script file and back-office batch file)
    2012-05-09 23:52:21下载
    积分:1
  • Exercise4
    AES TSAPI Retrieve Event in Non-blocking Mode
    2019-05-07 20:04:58下载
    积分:1
  • CodedLOCK
    基于FPGA的电子密码锁设计与实现,语言是VHDL语言,有注释(FPGA-based design and implementation of electronic locks, language is VHDL language, annotated)
    2013-08-27 21:37:06下载
    积分:1
  • widgets
    CSS配合jquery制作完美漂亮的时钟,貌似在IE8下时钟不能获取时间啊!支持ie9、chrome、safari、firefox、opera (Chrome显示效果最佳,IE9下时钟无法工作)日历和骰子是原创,CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错,圆形时钟就差点了,也希望一起交流,共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)
    2014-10-31 09:25:37下载
    积分:1
  • gam7
    FPGA Implementation ofLow Power 64-Point Radix-4 FFT Processor for OFDM System
    2011-01-22 11:45:44下载
    积分:1
  • 杰姆斯阿姆斯壮的VHDL设计,源代码
    James Armstrong VHDL Design , source code
    2022-09-04 01:55:03下载
    积分:1
  • m_xulie
    这是用verilogHDL写的m序列发生器,简单易用,代码非常易读(It is written verilogHDL m sequence generator, easy to use, the code is very easy to read)
    2015-05-27 20:21:26下载
    积分:1
  • 696518资源总数
  • 105300会员总数
  • 3今日下载