-
SPI接口的AD芯片配置
由FPGA模拟生成SPI接口时序,完成AD芯片的配置,AD芯片为ADI公司的ad9852,程序配置的较为详细,适合使用类似AD芯片开发者参考
- 2022-09-28 05:20:03下载
- 积分:1
-
data_swith
verilog 代码实现串并转换,有延迟(Verilog code and string conversion, delay)
- 2011-07-31 23:58:17下载
- 积分:1
-
newViterbi217
基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误(IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct)
- 2020-06-29 08:40:01下载
- 积分:1
-
DDS波形发生器
DDS波形生成器verilog语言书写(FPGA型号cy4以上)(DDS generate verilog)
- 2017-07-17 22:25:11下载
- 积分:1
-
时序分析
XILINX 时序约束使用指南笔记 ——时序约束介绍 时序约束方法 时序约束原则等(XILINX time series constraints use guide notes -- time series constraints introducing time series constraint principles, etc.)
- 2017-12-21 11:37:56下载
- 积分:1
-
APB总线slave
完成APB slave 的单次寄存器读写控制,相同时终域完成,简单操作
- 2023-05-06 10:10:04下载
- 积分:1
-
sqr
VHDL CODE FOR SQUARE WAVE GENERATOR
- 2014-01-22 17:14:20下载
- 积分:1
-
VHDL-TESTBENCH
VHDL TESTBENCH书写规范,对学习FPGA的同学很有帮助,掌握仿真语言书写规范。(VHDL TESTBENCH description of the norms, the students learn FPGA helpful, master the language of simulation techniques)
- 2016-12-15 21:33:24下载
- 积分:1
-
turbo_dinter
说明: 电网协议信道解交织器设计FPGA实现,适用于PB16的宽带电力线载波通信(Grid protocol channel deinterleaver design FPGA implementation, suitable for PB16 broadband power line carrier communication)
- 2020-05-08 15:53:18下载
- 积分:1
-
synthesis-bandstop-filters
本例介绍直接合成带阻滤波器的方法,n阶滤波器能实现n个传输零点(A direct synthesis technique of a new class of bandstop
coupled resonator elliptic filters is presented. Two different
coupling schemes, which both include source–load coupling are
used. The first coupling and routing scheme is the standard folded
structure used in implementing bandpass elliptic filters with
transmission zeros using resonators.)
- 2013-03-12 18:19:01下载
- 积分:1