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16QAM调制与解调的FPGA实现
该源代码是实现14路并行的16QAM的调制,以及解调,其中还包含测试文件,已经在altera FPGA上面实现了其正确性,可以直接拿来使用。
- 2022-06-11 17:29:04下载
- 积分:1
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LowPassFilter
说明: 内部含3个模块,使用DDS产生200k与500k的正弦波,两者相加后过数字低通滤波(通带0-200k,阻带400k以上),并将波形输出,实测FFT分析中看不到500k分量。其中数字滤波器采用MATLAB设计(FIR+等波纹,阻带衰减-80dB)(There are three modules in the system. DDS is used to generate 200K and 500K sine waves. After adding the two modules, the digital low-pass filter (passband 0-200k, stopband above 400k) is used, and the waveform is output. 500K component can not be seen in the actual FFT analysis. The digital filter is designed by MATLAB (FIR + equal ripple, stopband attenuation - 80dB))
- 2020-09-09 14:21:01下载
- 积分:1
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zuheshixu
说明: 组合时序电路的小例子,移位和数据选择器的代码,以及测试文件(Small examples of combinational sequential circuits, code for shift and data selectors, and test file.)
- 2019-12-12 15:13:50下载
- 积分:1
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verilog_rtl
关于LDPC解码的verilog程序,包含设计代码和验证环境(LDPC decoding on verilog procedures, including the design code and verification environment)
- 2015-10-29 15:42:03下载
- 积分:1
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CCMU
代码是一个复数乘法器,两个复数相乘,只用到了2个实数相乘,运算量少(Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less)
- 2011-11-04 11:56:47下载
- 积分:1
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verilog下miller米勒编解码
这个是verilog下miller米勒编解码,小实验。直接运行即可,将时间轴拉大即可看到具体波形。
- 2023-05-26 19:50:04下载
- 积分:1
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FloatPoint Arithmetic
Float Point Add, Multiply, and Divide arithmetic. You can change and modify the add block and reuse it in FPGA or ASIC chip. The running clock is dependent of the technology you used in the ASIC.
- 2022-06-13 03:38:57下载
- 积分:1
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sos_module
用FPGA实现sos摩尔密码,即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”,“画”和“间隔”。而 control_module.v 是一个简单的定时触发器,每一段时间都会使能sos_module.v。(Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password, painting and intervals. And control_module.v is a simple timer triggers, each period of time will enable sos_module.v.)
- 2016-09-20 16:26:29下载
- 积分:1
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UC1608-24064
UC1608 24064驱动 COG LCD驱动程序(UC1608 24064)
- 2011-09-09 08:24:24下载
- 积分:1
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普通的加法器
利用基本全加器的逻辑表达式,写单个加法器模块。
通过模块例化,直接级联加法器,同时在输入输出端口加入寄存器。
最后可以实现不考虑进位的加法。
- 2022-04-09 18:39:27下载
- 积分:1