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MPEG
MPEG-2TS 流嵌入控制数据的设计，设计的要求是用控制数据替换MPEG-2 TS 流中的空帧-MPEG-2TS control data stream embedded in the design, the design requirements is to control data to replace MPEG-2 TS stream of the air frame
- 2022-01-24 14:30:49下载
- 积分：1
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基于EDA技术的数字密码锁源程序代码,大学实训用的着
基于EDA技术的数字密码锁源程序代码,大学实训用的着-EDA-based Digital code lock source code, used by the University Training
- 2022-02-12 12:31:41下载
- 积分：1
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traffic_lights
用Verilog实现的交通信号灯控制，主干道和支路通行的时间不相等(Using Verilog implementation of traffic signal control, the trunk road and the slip is not the same passage of time)
- 2009-03-28 18:31:31下载
- 积分：1
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cpu_code_8051
vhdl code for 8051 processor
- 2010-06-25 15:16:07下载
- 积分：1
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SeggerEval_LPC2478
emWin 在LPC2478上实现LCD的高性能显示(emWin to achieve high-performance LCD display in the LPC2478)
- 2012-08-04 13:54:29下载
- 积分：1
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codes
EKG SIGNAL PROCESSING THROUGH CORDIC
- 2013-09-29 01:46:17下载
- 积分：1
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keyscan
用verilog语言写的简单的键盘扫描代码，适合初学者，用alter的软件编写的程序代码。(Using verilog language to write simple keyboard scan code, suitable for beginners, with alter software program written code.)
- 2013-09-13 22:59:11下载
- 积分：1
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一个基于fpga的源程序，对于初始接住的人来说很有帮助
一个基于fpga的源程序，对于初始接住的人来说很有帮助-FPGA-based source for the initial very helpful for those who catch
- 2023-01-04 08:05:03下载
- 积分：1
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uart-for-fpga
Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA.
Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit!
The UART controller was simulated and tested in hardware.
- 2020-06-24 22:00:02下载
- 积分：1
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state-machine
一个简单的用verilog实现的售货机状态机设计，内有word介绍设计的原理(A simple realization of a vending machine with verilog state machine design, there are design principles introduced word)
- 2021-01-20 23:48:42下载
- 积分：1
