uart-for-fpga

代码说明：

  Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

文件列表：

uart-for-fpga-master, 0 , 2018-12-21
uart-for-fpga-master\LICENSE, 1079 , 2018-12-21
uart-for-fpga-master\README.md, 2786 , 2018-12-21
uart-for-fpga-master\example, 0 , 2018-12-21
uart-for-fpga-master\example\quartus, 0 , 2018-12-21
uart-for-fpga-master\example\quartus\uart_loopback.qpf, 503 , 2018-12-21
uart-for-fpga-master\example\quartus\uart_loopback.qsf, 1362 , 2018-12-21
uart-for-fpga-master\example\timing_constraints.sdc, 524 , 2018-12-21
uart-for-fpga-master\example\uart_loopback.vhd, 2028 , 2018-12-21
uart-for-fpga-master\example\uart_loopback_tb.vhd, 2772 , 2018-12-21
uart-for-fpga-master\rtl, 0 , 2018-12-21
uart-for-fpga-master\rtl\comp, 0 , 2018-12-21
uart-for-fpga-master\rtl\comp\uart_debouncer.vhd, 2518 , 2018-12-21
uart-for-fpga-master\rtl\comp\uart_parity.vhd, 2057 , 2018-12-21
uart-for-fpga-master\rtl\comp\uart_rx.vhd, 8694 , 2018-12-21
uart-for-fpga-master\rtl\comp\uart_tx.vhd, 9064 , 2018-12-21
uart-for-fpga-master\rtl\uart.vhd, 5475 , 2018-12-21
uart-for-fpga-master\sim, 0 , 2018-12-21
uart-for-fpga-master\sim\sim.tcl, 843 , 2018-12-21
uart-for-fpga-master\sim\uart_tb.vhd, 3063 , 2018-12-21