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Xilinx CPLD源代码，使用XC9500系列CPLD,驱动液晶
Xilinx CPLD源代码，使用XC9500系列CPLD,驱动液晶-Xilinx CPLD source code, use the XC9500 series CPLD, LCD Driver
- 2023-03-07 15:05:03下载
- 积分：1
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buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键...
buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键-buffer_display is 4X4KEYPAD output module. It showed six consecutive Press
- 2022-12-12 05:35:03下载
- 积分：1
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fir4btp
4tap FIR filter in verilog code
- 2014-01-13 22:30:58下载
- 积分：1
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VHDL_biss
FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)
- 2021-03-15 19:19:22下载
- 积分：1
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QPSK_1
QPSK调制，QPSK仿真误码率,QPSK理论误码率 , QPSK仿真误比特率 , QPSK理论误比特率 (QPSK modulation, the signal-to-noise ratio)
- 2020-12-06 19:29:22下载
- 积分：1
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采用硬件描述语言Verilog HDL实现人回答功能，H.
用verilog hdl硬件描述语言实现多人抢答器功能，有计时，计分，报警等功能。-Using hardware description language verilog hdl people realize Answer feature, have timing, scoring and alarm functions.
- 2022-03-17 02:15:20下载
- 积分：1
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modulationshaped
基带数字信号通过成形滤波（选用升余弦滚降函数）然后进行载波调制(Base-band digital signal through the shaping filter (raised cosine roll-off optional function) and then proceed to carrier modulation)
- 2007-10-31 15:27:18下载
- 积分：1
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Baseband_line_code
基于VHDL语言的基带线路码产生电路设计（毕业论文），内涵完整的源代码(Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code)
- 2010-07-03 22:38:09下载
- 积分：1
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Modulation
产生长度为100的随机二进制序列
发送载波频率为10倍比特率，画出过采样率为100倍符号率的BPSK调制波形（前10个比特） ，及其功率谱
相干解调时假设收发频率相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1（其余为0），或连续12个1 （其余为0） ，分别画出两种滤波器下的y(t)，及判决输出（前10个比特）
接收载波频率为10.05倍比特率，初相位相同，画出x(t) 的波形，假设低通滤波器的冲激响应为连续10个1，画出两种滤波器下的y(t)，及判决输出（前20个比特）
采用DPSK及延时差分相干解调，载波频率为10倍比特率，画出a, b, c, d点的波形（前10个比特）
DPSK及延时差分相干解调，载波频率为10.25倍比特率时，画出a, b, c, d点的波形（前10个比特）
DPSK及延时差分相干解调，载波频率为10.5倍比特率时，画出a, b, c, d点的波形（前10个比特）
(Produce random binary sequence of length 100
The transmission carrier frequency is 10 times the bit rate, draw a sampling rate of 100 times the symbol rate of the BPSK modulation waveform (first 10 bits), its power spectrum
Coherent demodulation of assuming the same as the phase of the transmitting and receiving frequencies, and draw the waveform x (t), assuming that the impulse response of the low pass filter 10 consecutive 1 (the remainder is 0), or 12 consecutive 1 (the remainder is 0), y (t) is drawn under the two filters respectively, and the decision output (10 bits)
The received carrier frequency is 10.05 times the bit rate, the same initial phase, draw the waveform x (t), assuming that the impulse response of the low pass filter of 10 consecutive 1, shown under two filter y (t), and decision output (20 bits)
DPSK and delay differential coherent demodulation, the carrier frequency is 10 times the bit rate, draw a, b, c, d point of the waveform (first 10 bits)
DPSK and delay)
- 2020-12-14 08:19:14下载
- 积分：1
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Signal
基于FPGA的DDS相位累加器，连接至存有波形数据的rom后再接至DA可以输出对应的波形(abcdefghijklmnopqrstuvwxyz)
- 2018-05-10 15:19:05下载
- 积分：1
