VHDL_biss

代码说明：

  FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)

文件列表：

altera_vhdl_support.vhd
assignment_defaults.qdf
Auslese_flag.vhd
biss.qpf
biss.qws
button.vhd
cmp_state.ini
cpu.ocp
cpu.vhd
cpu_gen_log_0.txt
cpu_jtag_debug_module.vhd
cpu_jtag_debug_module_wrapper.vhd
cpu_ociram_default_contents.mif
cpu_test_bench.vhd
Dataread.vhd
DataWrite.vhd
db
..\MultiCycleData.asm.qmsg
..\MultiCycleData.cbx.xml
..\MultiCycleData.cmp.rdb
..\MultiCycleData.db_info
..\MultiCycleData.eco.cdb
..\MultiCycleData.fit.qmsg
..\MultiCycleData.hier_info
..\MultiCycleData.hif
..\MultiCycleData.map.hdb
..\MultiCycleData.map.qmsg
..\MultiCycleData.pre_map.hdb
..\MultiCycleData.psp
..\MultiCycleData.rtlv.hdb
..\MultiCycleData.rtlv_sg.cdb
..\MultiCycleData.rtlv_sg_swap.cdb
..\MultiCycleData.sgdiff.cdb
..\MultiCycleData.sgdiff.hdb
..\MultiCycleData.sld_design_entry.sci
..\MultiCycleData.sld_design_entry_dsc.sci
..\MultiCycleData.syn_hier_info
..\MultiCycleData.tan.qmsg
..\MultiCycleData_cmp.qrpt
..\small.db_info
epcs_controller.vhd
epcs_controller_boot_rom.hex
geberclock.bsf
geberclock.vhd
ic_tag_ram.mif
IDundADRundWNR.vhd
jtag_uart.vhd
led.vhd
length.vhd
Mcd.vhd
Modus.vhd
MultiCycleData.asm.rpt
MultiCycleData.bsf
MultiCycleData.done
MultiCycleData.fit.eqn
MultiCycleData.fit.rpt
MultiCycleData.fit.summary
MultiCycleData.flow.rpt
MultiCycleData.map.eqn
MultiCycleData.map.rpt
MultiCycleData.map.summary
MultiCycleData.pin
MultiCycleData.pof
MultiCycleData.qpf
MultiCycleData.qsf
MultiCycleData.qws
MultiCycleData.sof
MultiCycleData.tan.rpt
MultiCycleData.tan.summary
MultiCycleData.vhd
out_directory_tmp.txt.tmp
Pio_lm74.vhd
Pllx3.bsf
Pllx3.inc
Pllx3.vhd
Positionsdaten.vhd
Regclock.bsf
Regclock.vhd
register_clock.bsf
register_clock.vhd
Register_mode
.............\.cdtbuild
.............\.cdtproject
.............\.project
.............\application.stf
.............\Debug
.............\readme.txt
.............\Register_Modus.c
Register_Mode.bsf
Register_Mode.vhd
rf_ram_a.mif
rf_ram_b.mif
rs485_aus.vhd
rs485_ein.vhd
sdram.vhd
sdram_test_component.vhd
SensorMode
..........\.cdtbuild
..........\.cdtproject
..........\.project