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altera_fft
verilog实际例子，非常适合初学者学习(verilog practical examples, very suitable for beginners to learn)
- 2020-12-06 16:49:22下载
- 积分：1
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CODE_VHDL_COUNTING 0 到 9，使用按钮 (Đếm 慈 0 đến 9 hiển 施耐 1 带领 7 đoạn sử dụng nút nhấn để điều khiển)
CODE_VHDL_COUNTING 0 到 9，使用按钮 (Đếm 慈 0 đến 9 hiển 施耐 1 带领 7 đoạn sử dụng nút nhấn để điều khiển)
Với bài này tôi sử dụng một nút nhất để một nút nhấn đế bắt đầu đếm dữ liệu 将重置。
- 2022-07-25 16:14:59下载
- 积分：1
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i2sound_volume_control
通过代码控制音频编/解码硬件芯片WM8731，
通过按键控制音频输出的音量(Audio codec hardware chip WM8731 is controlled by code, and audio output volume is controlled by keys.)
- 2018-11-27 14:39:51下载
- 积分：1
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imply logic
由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)
- 2019-04-24 15:42:24下载
- 积分：1
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bishe
基于FPGA 的VGA波形显示，dds产生三角波正弦波(Vga waveform display based on FPGA, using DDS to generate sinusoidal triangular wave)
- 2018-12-12 11:26:37下载
- 积分：1
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DDC_Ver1.0
数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值(Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value)
- 2010-08-04 18:33:14下载
- 积分：1
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Comparator for Quartus
Comparator for Quartus
- 2022-06-21 21:12:14下载
- 积分：1
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DDSVHDLCODE
本人收集的多个VHDL语言编写的正弦波发生器以及SPWM程序。(I collected multiple VHDL language of sine wave generator SPWM program.)
- 2021-04-06 22:39:02下载
- 积分：1
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Desktop
说明： qpsk的fpga实现，包含调制和解调部分，使用verilog语言(FPGA implementation of QPSK)
- 2019-03-16 02:52:26下载
- 积分：1
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irdecode
自己编写的红外解码子程序，但CPU资源占用较高，作教学示范用途。(prepared their infrared decoding routines, but higher occupancy CPU resources for teaching demonstration purposes.)
- 2006-11-05 13:51:28下载
- 积分：1
