AD9250 204b Verilog源码

代码说明：

说明：  AD9250是一款双通道14位ADC，最高采样速率250 MSPS，JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)

文件列表：

AD9250 204b Verilog源码, 0 , 2021-04-14
AD9250 204b Verilog源码\adi_common_v1_00_a, 0 , 2021-04-14
AD9250 204b Verilog源码\adi_common_v1_00_a\hdl, 0 , 2021-04-14
AD9250 204b Verilog源码\adi_common_v1_00_a\hdl\verilog, 0 , 2021-04-14
AD9250 204b Verilog源码\adi_common_v1_00_a\hdl\verilog\cf_gtx_es_if.v, 27440 , 2013-03-12
AD9250 204b Verilog源码\adi_common_v1_00_a\hdl\verilog\cf_gtx_es_wr.v, 9605 , 2013-03-12
AD9250 204b Verilog源码\adi_common_v1_00_a\hdl\verilog\cf_jesd_align_2.v, 3759 , 2013-04-03
AD9250 204b Verilog源码\adi_common_v1_00_a\hdl\verilog\cf_jesd_mon.v, 8786 , 2013-03-12
AD9250 204b Verilog源码\adi_common_v1_00_a\hdl\verilog\cf_mem.v, 3216 , 2013-03-11
AD9250 204b Verilog源码\axi_ad9250_v1_00_a, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\data, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\data\_axi_ad9250_xst.prj, 1712 , 2012-09-06
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\data\axi_ad9250_v2_1_0.mpd, 3626 , 2013-04-02
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\data\axi_ad9250_v2_1_0.pao, 1098 , 2012-09-06
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\hdl, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\hdl\verilog, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\hdl\verilog\cf_ad9250.v, 11713 , 2013-04-02
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\hdl\verilog\cf_adc_if.v, 5793 , 2013-04-03
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\hdl\verilog\cf_dma_wr.v, 16109 , 2013-01-12
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\hdl\verilog\cf_mem.v, 3216 , 2012-08-08
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\hdl\verilog\cf_pnmon.v, 9874 , 2013-04-03
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\hdl\verilog\user_logic.v, 6783 , 2013-04-02
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\hdl\vhdl, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\hdl\vhdl\axi_ad9250.vhd, 10122 , 2013-04-02
AD9250 204b Verilog源码\axi_ad9250_v1_00_a\regmap.txt, 5130 , 2012-08-08
AD9250 204b Verilog源码\axi_clkgen_v1_00_a, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_clkgen_v1_00_a\data, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_clkgen_v1_00_a\data\_axi_clkgen_xst.prj, 1488 , 2012-05-03
AD9250 204b Verilog源码\axi_clkgen_v1_00_a\data\axi_clkgen_v2_1_0.mpd, 2884 , 2012-06-18
AD9250 204b Verilog源码\axi_clkgen_v1_00_a\data\axi_clkgen_v2_1_0.pao, 565 , 2012-05-03
AD9250 204b Verilog源码\axi_clkgen_v1_00_a\hdl, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_clkgen_v1_00_a\hdl\verilog, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_clkgen_v1_00_a\hdl\verilog\cf_clkgen.v, 13841 , 2013-01-23
AD9250 204b Verilog源码\axi_clkgen_v1_00_a\hdl\verilog\user_logic.v, 6102 , 2012-08-08
AD9250 204b Verilog源码\axi_clkgen_v1_00_a\hdl\vhdl, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_clkgen_v1_00_a\hdl\vhdl\axi_clkgen.vhd, 9468 , 2012-08-08
AD9250 204b Verilog源码\axi_clkgen_v1_00_a\regmap.txt, 4434 , 2012-08-08
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\cf_jesd_core.cdc, 5252 , 2013-03-04
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\data, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\data\_axi_jesd204b_rx2_xst.prj, 3339 , 2013-04-03
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\data\axi_jesd204b_rx2_v2_1_0.bbd, 490 , 2012-07-28
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\data\axi_jesd204b_rx2_v2_1_0.mpd, 5385 , 2013-04-03
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\data\axi_jesd204b_rx2_v2_1_0.pao, 1117 , 2013-04-03
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\hdl, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\hdl\verilog, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\hdl\verilog\jesd204b_rx2_gtwizard_v2_1.v, 23958 , 2012-07-31
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\hdl\verilog\jesd204b_rx2_gtwizard_v2_1_gt.v, 39866 , 2013-02-26
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\hdl\verilog\jesd204b_rx2_gtwizard_v2_1_top.v, 22012 , 2012-09-10
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\hdl\verilog\jesd204b_rx2_top.v, 24583 , 2013-04-03
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\hdl\verilog\user_logic.v, 8374 , 2013-04-03
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\hdl\vhdl, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\hdl\vhdl\axi_jesd204b_rx2.vhd, 16342 , 2013-04-03
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\netlist, 0 , 2021-04-14
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\netlist\jesd204b_rx2.xco, 1530 , 2012-09-06
AD9250 204b Verilog源码\axi_jesd204b_rx2_v1_00_a\regmap.txt, 7917 , 2013-03-04
AD9250 204b Verilog源码\util_jesdbuf_v1_00_a, 0 , 2021-04-14
AD9250 204b Verilog源码\util_jesdbuf_v1_00_a\data, 0 , 2021-04-14
AD9250 204b Verilog源码\util_jesdbuf_v1_00_a\data\util_jesdbuf_v2_1_0.mpd, 981 , 2012-09-28
AD9250 204b Verilog源码\util_jesdbuf_v1_00_a\data\util_jesdbuf_v2_1_0.pao, 417 , 2012-09-10
AD9250 204b Verilog源码\util_jesdbuf_v1_00_a\hdl, 0 , 2021-04-14
AD9250 204b Verilog源码\util_jesdbuf_v1_00_a\hdl\vhdl, 0 , 2021-04-14
AD9250 204b Verilog源码\util_jesdbuf_v1_00_a\hdl\vhdl\util_jesdbuf.vhd, 5117 , 2013-01-12