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数字波形存储器VHDL源码,基于Quartus II开发。
数字波形存储器VHDL源码,基于Quartus II开发。-Digital waveform memory VHDL source code, based on the Quartus II development.
- 2022-01-26 14:31:04下载
- 积分:1
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ps2interface
one of example about hardware design language
- 2009-12-25 07:17:18下载
- 积分:1
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a
说明: 用verilog实现除法器,调用了ip核,不仅有源代码,还有测试程序的时序编写(verilog ise divider)
- 2013-07-21 15:03:31下载
- 积分:1
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my_kmp_matching
说明: KMP算法的Verilog HDL实现,模式串从模块的外部输入,计算next函数,然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。(Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment for the Quartus II 8.0 Web Edition.)
- 2011-03-14 09:28:01下载
- 积分:1
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dac9747
主要完成ADI公司的DAC(数字-模拟转换器)AD9747的SPI接口及寄存器配置(Mainly to complete ADI' s DAC (digital- analog converter) SPI interface to configure the AD9747 and the register of)
- 2014-06-03 11:00:43下载
- 积分:1
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ROM模块,功能在于,是创建一个简易的rom模块
ROM模块,功能在于,是创建一个简易的rom模块-rom
- 2022-03-31 16:48:46下载
- 积分:1
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29_ad9226_test
用Verilog编写ad_9866的相应程序,在FPGA上实现相应功能(The corresponding program of ad_9866 is written with Verilog, and the corresponding functions are realized on the FPGA.)
- 2019-06-24 16:43:27下载
- 积分:1
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md5
MD5 算法在Xilinx FPGA上的实现,希望对大家有用。(MD5 algorithm in Xilinx FPGA Implementation, in the hope that useful to everyone.)
- 2021-04-19 15:18:51下载
- 积分:1
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generateCAcode
gps C/A码生成
生成gps32颗卫星伪码,方便,经过测试(gps C/A code generation to generate pseudo-code satellites gps32, convenient and tested)
- 2021-05-13 04:30:02下载
- 积分:1
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基于FPGA的神经网络硬件实现中的关键问题研究,适合用fpga研究神经网络的工程人员参考...
基于FPGA的神经网络硬件实现中的关键问题研究,适合用fpga研究神经网络的工程人员参考-FPGA-based hardware implementation of neural networks in the study of key issues for research with neural networks fpga reference works
- 2022-04-17 01:07:47下载
- 积分:1