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xvrware图书馆Xilinx Inc.
XVRWARE Library Xilinx Inc.
The XVRWARE Synthesis library provides macros and synthesis examples for constructing TMR circuits in VHDL for the Virtex architecture
- 2023-07-20 21:50:04下载
- 积分：1
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简单电子玩具的感知模块程序设计,通过外部输入信号改变内部信号.从而改变玩具的状态
简单电子玩具的感知模块程序设计,通过外部输入信号改变内部信号.从而改变玩具的状态-simple electronic toys perception module programming, through external input signal a change in the internal signal. In order to change the state of toys
- 2022-03-05 12:17:08下载
- 积分：1
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用于sopc builder添加组件用的ps/2
键盘 ipcore
用于sopc builder添加组件用的ps/2
键盘 ipcore-Sopc builder used to add components used ps/2 keyboard IPCore
- 2022-03-12 14:54:04下载
- 积分：1
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ASIC_LIB
ASIC设计中常用的运算模块，如加减，常系数乘法，截断，饱和等。(some modules used in ASIC design.)
- 2010-03-10 15:52:28下载
- 积分：1
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二
两路十字路口的交通灯控制的VHDL源码，毕业设计，-Two-way traffic lights at the crossroads of the VHDL source code control, graduation design,
- 2022-04-18 12:48:42下载
- 积分：1
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CPU代码
CPU代码-VHDL语言，实现了CPU的基本功能。-CPU code-VHDL language, the realization of the basic functions of the CPU.
- 2022-02-02 11:14:11下载
- 积分：1
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tsobbellh
这是我本人自己开发的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合与与仿真，并在FPGA上测试过。能进行修改支持其他大小图像的sobeel边缘检测，同时还能实现其它的图像模块化处理算法，例如高斯滤波，平滑等。
(This is my own development vhd file, can be used for 256* 256 size image sobel edge detection under QuartusII or MaxplisII synthesis and with simulation, and tested on FPGA. Can be modified to support other sobeel size image edge detection, while still achieving other image the modular processing algorithms, such as Gaussian filtering and smoothing.)
- 2012-08-23 22:17:19下载
- 积分：1
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altera 公司的15IP源码
亲自测试还不错 有DIV, CONTER
altera 公司的15IP源码
亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER
- 2022-03-13 02:56:46下载
- 积分：1
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Harris-algorithm-based-on-FPGA
在利用FPGA的并行处理能力应对高速数据和去做复杂的数据处理时，对一些较为复杂或者重复性工作模块多的情况下，算法资源就需要进行预评估。有效的资源预评估不仅可以在芯片选型上有益，还可以对程序有较详细的估计，在硬件不变的前提下能够选择更好的算法优化。本文着重在Harris算法在FPGA的实现以及在移植之前对其占用的FPGA资源进行预评估。(Response to high-speed data and do complex data processing in the FPGA parallel processing capabilities, to cope with some of the more complex or repetitive tasks module，it is necessary to pre-assessment algorithm resources. Resources pre-assessment can not only be useful in the chip selection, but also be a more detailed estimate of the program to be able to choose a better algorithm optimization in the same premise hardware. This article focuses on the pre-assessment in the Harris algorithm in the FPGA implementation and its FPGA resources occupied prior to transplantation.)
- 2013-02-28 15:41:39下载
- 积分：1
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ad7606
ADC7606的驱动代码，采用verilog实现(ADC7606 driver code, using Verilog to achieve)
- 2021-03-30 09:39:10下载
- 积分：1
