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常用小程序一应俱全
一些常见的小模块,自己写的,可能不是特别好,仅供参考,主要是分频器、计数器和数码管的显示
- 2022-07-24 04:15:27下载
- 积分:1
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project_first
说明: basys3的数字钟,可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)
- 2019-06-18 10:37:53下载
- 积分:1
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dgnszsz
多功能数字钟,在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)
- 2013-09-20 10:20:31下载
- 积分:1
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src
假设每个从设备中有可访问APB寄存器16个,位宽均为32比特,16个寄存器的访问地址计算方式为 基址 + 寄存器编号左移2位(byte 偏移)(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)
- 2020-12-15 13:49:14下载
- 积分:1
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是用VHDL语言写的对A/D转换模块的控制程序,希望对大家有帮助。...
是用VHDL语言写的对A/D转换模块的控制程序,希望对大家有帮助。-VHDL language is used on the A/D conversion module control procedures, in the hope that everyone has to help.
- 2023-05-25 06:40:03下载
- 积分:1
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fir
用窗函数法设计一个线性相位FIR数字低通滤波器,用理想低通滤波器作为逼近滤波器,通带截止频率为0.2 ,阻带截止频率为0.4 ,阻带衰减不小于-40dB。(Window function method to design a linear phase FIR digital low-pass filter, as an ideal low-pass filter for approximation filter passband cutoff frequency of 0.2 stopband cutoff frequency of 0.4, the stop-band attenuation of less than-40dB.)
- 2012-09-24 13:54:07下载
- 积分:1
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AES_128
AES 128 bit with various device interface on FPGA
- 2021-03-09 17:59:27下载
- 积分:1
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URAT 部分VHDL源码 大家多多支持 哈哈
URAT 部分VHDL源码 大家多多支持 哈哈 -VHDL source URAT part of U.S. support of Haha
- 2022-02-20 22:56:56下载
- 积分:1
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jianpan
说明: 一个简单的键盘接口模块程序,对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)
- 2020-06-24 02:00:02下载
- 积分:1
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mul
实现有限域中乘法,输入二个普通二级制数,输出在本原多项式的乘法结果(Achieve limited multiplication field, enter the number of two-tier system of two ordinary output in primitive polynomial multiplication results)
- 2014-01-12 22:52:38下载
- 积分:1