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一种基于LUT的预失真方法。其中的一部分,有参考价值。
一种基于LUT的预失真方法。其中的一部分,有参考价值。-one method of DPD based on LUT
- 2022-06-30 17:35:36下载
- 积分:1
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DS1820
DS18B20温度传感器,用verilog语言实现(DS18B20 temperature sensor, with the verilog language)
- 2020-11-01 21:29:55下载
- 积分:1
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This is a use of the VHDL language Parallel to Serial procedures, In altera deve...
这是一个用VHDL语言编写的并口转串口程序,在altera开发系统下验证通过,运用于开发板与计算机之间的通信,源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communications, can provide a reference source
- 2022-03-23 13:41:19下载
- 积分:1
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stm32adc12路采集DMA
adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)
- 2020-06-19 06:20:01下载
- 积分:1
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一个在FPGA芯片上实现UART功能的vhdl源代码,提供了UART的集成
一个在FPGA芯片上实现UART功能的vhdl源代码,提供了UART的集成-an FPGA chip to achieve UART function vhdl source code, providing integrated UART
- 2022-01-21 03:04:04下载
- 积分:1
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16 floating
16卫浮点FFT算法的VHDL实现,有测试文件。-16 floating-point FFT algorithm Wei VHDL realize, have the test paper.
- 2023-03-07 14:45:03下载
- 积分:1
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altera公司cpld的原理图库(protel格式)
altera公司cpld的原理图库(protel格式)-sch.lib about altera s cpld.
- 2022-03-18 02:53:20下载
- 积分:1
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Hardware-CNN-master
说明: Convolutional neural network code for fpga
- 2019-02-27 15:21:22下载
- 积分:1
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shuzishizhong
这是基于verilog hdl的数字时钟源代码,能够实现时分秒的计时,可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)
- 2013-12-10 22:21:55下载
- 积分:1
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3P3_wimdow
图像插值算法,窗口为3*3,用于图像的除去死点,以及提高清晰度或者使图像柔和(3*3 window)
- 2012-02-28 15:36:02下载
- 积分:1