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基于Verilog 的电子日历与电子时钟程序，可以进行调日期、星期、时间的分钟与小时，通过几种模式来显示日历与时间。...
基于Verilog 的电子日历与电子时钟程序，可以进行调日期、星期、时间的分钟与小时，通过几种模式来显示日历与时间。-Verilog-based electronic calendar and e-clock procedures, can be adjusted date, week, time of minutes and hours, through several models to display a calendar and time.
- 2022-02-02 07:03:46下载
- 积分：1
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EDAandVHDL
EDA技术与VHDL课件，利用EDA技术进行电子系统设计(EDA technology and VHDL courseware, the use of EDA technology for electronic system design)
- 2009-03-04 15:34:53下载
- 积分：1
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primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used stora...
本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
- 2022-07-07 05:54:22下载
- 积分：1
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jiaozhijiejiaozhi
VHDL代码完成行列交织与解交织的功能实现(the realization of interleaver on VHDL language)
- 2020-07-17 15:08:49下载
- 积分：1
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div_fru
介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。(Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not a problem.)
- 2010-06-17 21:52:55下载
- 积分：1
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一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (mo...
一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
- 2022-08-21 18:15:23下载
- 积分：1
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CPUdesign
说明： 计算机组成原理实验多时钟周期CPU设计，包含VHDL代码的设计，实验电路图，实验详细截图。(Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.)
- 2020-09-07 19:28:05下载
- 积分：1
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实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。...
实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.
- 2022-12-20 07:25:03下载
- 积分：1
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ddr2_controller
DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.(DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.)
- 2010-02-23 09:16:50下载
- 积分：1
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digital_clock
说明： 数字钟通过verilog实现，并且支持Modelsim仿真，通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)
- 2020-06-18 05:00:02下载
- 积分：1
