登录
首页 » VHDL » 实验课的作业,包括半加器、全加器、加/减法器,使用逻辑图和VHDl描述,包括分析和报告。...

实验课的作业,包括半加器、全加器、加/减法器,使用逻辑图和VHDl描述,包括分析和报告。...

于 2022-12-20 发布 文件大小:59.31 kB
0 107
下载积分: 2 下载次数: 1

代码说明:

实验课的作业,包括半加器、全加器、加/减法器,使用逻辑图和VHDl描述,包括分析和报告。-experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 托马斯的教科书Verilog。Verilog的托马斯在该领域的著名…
    Thomas课本中的verilog例子。Thomas的verilog在可编程期间领域很有名-Thomas textbook example of verilog. Verilog Thomas in the field during the famous programmable
    2022-03-07 05:06:40下载
    积分:1
  • verilog hdl教程135例:verilog hdl语言类似于C语言,便于学习。本文档带有源代码,11...
    verilog hdl教程135例:verilog hdl语言类似于C语言,便于学习。本文档带有源代码,11-12章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code 11-10-12 Cap
    2022-04-21 11:48:36下载
    积分:1
  • SPWM
    利用FPGA内核产生SPWM波,并且频率可调(The FPGA kernel is used to generate SPWM waves, and the frequency is adjustable)
    2020-12-08 20:19:19下载
    积分:1
  • chengxu_jieshou
    nrf24l01发送代码,verilog实现NRF24L01通信(NRF24L01 send code, Verilog to achieve NRF24L01 communication)
    2017-08-09 19:04:16下载
    积分:1
  • 32位元浮点数加法器,用于以VHDL编写的32位元CPU
    32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add
    2022-10-08 15:20:02下载
    积分:1
  • FPGA
    基于FPGA的数字系统设计,包含原理、工程应用和案例。(FPGA-based digital system design, including theory, engineering applications and cases.)
    2010-10-12 21:34:00下载
    积分:1
  • E VHDL数字电路设计
    VHDL数字电路设计的电子书,很好的学习材料-VHDL digital circuit design of e-books, very good learning materials
    2023-01-18 23:30:04下载
    积分:1
  • 4ASKmod2
    讲述4ASK的原理并附有matlab调制解调的源码。。。。。。。。。。 注:原来上传的4ASKmod.zip不要下(The principle tells 4ASK together with modulation and demodulation matlab source. . . . . . . . . . Note: The original upload 4ASKmod.zip not down)
    2013-07-10 00:01:10下载
    积分:1
  • bt656_decode
    说明:  将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)
    2021-01-28 10:38:35下载
    积分:1
  • counter4b
    Vivado同步计数器VHDL设计 具有异步复位和同步预置数功能 同步计数器同步计数器同步计数器(The Vivado synchronous counter VHDL is designed with asynchronous reset and synchronous preset function, synchronous counter, synchronous counter and synchronous counter.)
    2021-03-26 14:29:13下载
    积分:1
  • 696518资源总数
  • 105678会员总数
  • 22今日下载