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complex_timing_by_Primetime
用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)
- 2012-08-05 19:07:47下载
- 积分：1
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Wishbone dma ip core
Wishbone dma ip core
- 2022-01-26 04:18:15下载
- 积分：1
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我的学习经验，一种自适应分频及分频方法的实现，很好用的哦...
我的学习经验，一种自适应分频及分频方法的实现，很好用的哦-my learning experience, an adaptive frequency-frequency method and the realization of the good, oh
- 2022-02-03 01:08:00下载
- 积分：1
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VHDL USB2.0接口源码,内有说明,详细.
VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.
- 2022-04-29 19:53:42下载
- 积分：1
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FPGA realize for a good vga display routines, vhdl language.
针对FPGA一个实现vga显示的很好的例程，vhdl语言编写。-FPGA realize for a good vga display routines, vhdl language.
- 2022-01-24 09:45:51下载
- 积分：1
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cpu_easy
说明： ADD MOV MOVi SUB四指令cpu设计，qutartus，(Design of four-instruction CPU)
- 2019-05-13 11:44:49下载
- 积分：1
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拔河电路的设计
VHDL拔河电路的设计 基于cyclone V
VHDL拔河电路的设计 基于cyclone V
VHDL巴赫电路的设计 基于cyclone V
VHDL巴赫电路的设计 基于cyclone V
VHDL巴赫电路的设计 基于cyclone V
- 2022-07-16 17:58:29下载
- 积分：1
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04_uart_test
说明： 基于FPGA的串口发送和接收，使用的verlilog语言(Using Verilog serial port program, send and receive.)
- 2020-10-13 10:33:10下载
- 积分：1
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altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim
验证，文件中包含TEST...
altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim
验证，文件中包含TESTBENCH ，直接可用-altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available
- 2022-05-31 13:50:54下载
- 积分：1
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20190717 - Copy
this describes building spi block on verilog hdl and programming them on an fpga device
- 2020-06-21 21:40:02下载
- 积分：1
