登录
首页 » VHDL » the program have designed a PCM signal timing modules, including the CLK input,...

the program have designed a PCM signal timing modules, including the CLK input,...

于 2022-02-15 发布 文件大小:7.94 kB
0 59
下载积分: 2 下载次数: 1

代码说明:

该程序设计了一个产生PCM码流时序信号的模块,他包括输入端CLK,SET及输出端Q1,Q2,Q3-the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • NIOSII I2C接口模块及驱动程序,并含有测试程序。对想开发NIOS的工程师很有帮助...
    NIOSII I2C接口模块及驱动程序,并含有测试程序。对想开发NIOS的工程师很有帮助-NIOSII I2C interface module and driver, and contains the test procedures. NIOS of engineers want to develop useful
    2022-10-02 15:40:03下载
    积分:1
  • 1、ps/2键盘输入,通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当l...
    1、ps/2键盘输入,通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当lcd上显示满字符时,在按下按键自动清屏,从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait 1s in the lcd display characters input 3, which backspce keys on the keyboard was required to settle the screen 4, when the lcd display full of characters, the press the button automatically Qing-ping, from the first line of display.
    2022-01-31 12:27:49下载
    积分:1
  • 抢答器仿真
    本文件包括整个基于QuartusII实现的抢答器模块,其下包括各个分模块,实现效果较不错。                                                                                                                                                            
    2022-08-10 14:21:30下载
    积分:1
  • sine_cordic
    generate sine wave. Inputs : Amplitude, phasein, frequency
    2013-07-22 10:25:41下载
    积分:1
  • Combination of shots, quartus2 with the ModelSim FBI put together a detailed ste...
    结合截图,quartus2与ModelSim的联调的详细操作步凑,使初学者迅速上手-Combination of shots, quartus2 with the ModelSim FBI put together a detailed step-by-step operation, so that beginners get started quickly
    2022-03-22 02:04:39下载
    积分:1
  • 8051IP nuclear source code (VHDL). RAR
    8051IP 核源代码(VHDL).RAR-8051IP nuclear source code (VHDL). RAR
    2022-11-14 08:05:04下载
    积分:1
  • verilog HDL verilog HDL verilog HDL
    verilog HDL verilog HDL verilog HDL -verilog HDL
    2022-02-09 14:27:35下载
    积分:1
  • 用于实现两个数相加的vhdl代码,在相应的编译器中使用
    用于实现两个数相加的vhdl代码,在相应的编译器中使用-used to achieve the two summed VHDL code, the corresponding use of compiler
    2022-10-30 11:05:03下载
    积分:1
  • Application of VHDL language of the control procedures of traffic lights. Famili...
    应用VHDL语言编写交通灯的控制程序。 熟悉该语言的基本用法。-Application of VHDL language of the control procedures of traffic lights. Familiar with the basic use of the language.
    2023-07-22 01:45:04下载
    积分:1
  • ddr3_test
    说明:  通过循环读写DDR3内存,了解其工作原理和DDR3控制器的写法,由于DDR3控制复杂,控制器的编写难度高,这里笔者介绍XILINX的MIG控制器情况下应用,是后续音频、视频等需要用到SDRAM实验的基础。(Through reading and writing DDR3 memory circularly, we can understand its working principle and the writing method of DDR3 controller. Because of the complexity of DDR3 control, it is difficult to write the controller. Here, the author introduces the application of Xilinx's MIG controller, which is the basis of SDRAM experiment for subsequent audio and video.)
    2021-04-16 10:00:15下载
    积分:1
  • 696518资源总数
  • 104305会员总数
  • 11今日下载