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myfir
verilog编写的16阶升余弦滤波器 采用直接型结构实现 对方波进行滤波 输出波形 含testbench文件(order raised cosine filter verilog written 16 direct-type structure to achieve the other wave filtering the output waveform containing testbench file)
- 2020-10-05 16:47:44下载
- 积分：1
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Actel的core8051
Actel的core8051，周立功在做，免费版没有片上调试功能、无跟踪寄存器、无硬件触发器，代码不可见
- 2022-03-21 13:55:23下载
- 积分：1
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DDS_9858
这是一个调试好的AD9858的verilog配置代码对初学者很有帮助(This is a debugged Verilog code for AD9858, which is very helpful for beginners.)
- 2020-08-26 11:38:14下载
- 积分：1
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robot_7_31
使用Verilog HDL来控制机器人，六个高精密舵机，舵机运动非常流畅，舵机不抖动(FPGA to control the robot servo, six servos)
- 2012-12-07 11:11:02下载
- 积分：1
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qiangdaqi
本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)
- 2013-10-30 14:48:21下载
- 积分：1
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dds
基于DDS和SOPC的谐波信号发射器，拥有可调节的频率，阶段和谐波比例的谐波信号发射器由本文所设计。(Based on DDS and SOPC harmonic signal transmitter, with adjustable frequency, phase and harmonic proportion of harmonic signal transmitter designed by this article.)
- 2016-04-26 09:21:50下载
- 积分：1
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verilog fifo 代码
FIFO is a First-In-First-Out memory queue with control logic that manages
the read and write operations, generates status flags, and provides optional
handshake signals for interfacing with the user logic. It is often used to
control the flow of data between source and destination. FIFO can be
classified as synchronous or asynchronous depending on whether same clock
or different (asynchronous) clocks control the read and write operations. In
this project the objective is to design, verify and synthesize a synchronous
FIFO using binary coded read and write pointers to address the memory
array. FFIO full and empty flags are generated and passed on to source and
destination logics, respectively, to pre-empt any overflow or underflow of
data. In this way data integrity between source and destination is maintained.
The RTL description for the FIFO is
- 2022-05-22 08:44:13下载
- 积分：1
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ldpc_decoder_802_3an
802.3an ldpc码编码、译码设计，使用VERILOG hdl语言编写，包括测试代码，(802.3an ldpc code encoding, decoding the design, use of language VERILOG hdl, including test code,)
- 2021-02-14 15:29:49下载
- 积分：1
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pidd
VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)
- 2020-11-13 10:09:43下载
- 积分：1
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第十一部分 SDRAM读写例程
SDRAM即同步动态随机存储器，同步是指 Memory工作需要同步时钟，内部的命令的发送与数据的传输都以它为基准；动态是指存储阵列需要不断的刷新来保证数据不丢失；随机是指数据不是线性依次存储，而是自由指定地址进行数据读写。因为SDRAM具有存取速度大大高于FLASH存储器, 且具有读/写的属性, 因此SDRAM在系统中主要用于程序的运行空间,大数据的存储及堆栈。SDRAM是高速的动态随机存取存储器, 它的同步接口和完全流水线的内部结构使其拥有极大的数据速率, SDRAM的时钟频率可以达到100Mhz以上, 一片16位数据宽度的SDRAM的读写数据带宽达到1.6Gbit/s。
- 2022-05-09 09:53:40下载
- 积分：1
