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BaseLine1
this is an peak detection alguritm,in this matlab code u can clean base line noise to have clear ECG signal
- 2012-12-12 00:58:21下载
- 积分：1
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DDS_Dual_ports Verilog实现
DDS_Dual_ports Verilog实现，需要的可以下载实验，也可根据自身的需要修改，以求达到自身的目的
- 2022-02-26 19:19:42下载
- 积分：1
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AES_128
AES 128 bit with various device interface on FPGA
- 2021-03-09 17:59:27下载
- 积分：1
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ps2
使用verliog实现ps2键盘接口的驱动，通过altera cyclone 第四代验证通过(Use verliog implement ps2 keyboard interface driven by a fourth-generation verified by altera cyclone)
- 2015-12-17 16:28:38下载
- 积分：1
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Meyers-Wavelet.txt
Meyers wavelet. DWT VHDL.
- 2011-10-10 22:01:44下载
- 积分：1
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LED-clock-display
利用单片机控制LED时钟显示，以及闹钟，程序较大，但比较简单易懂。(LED clock display)
- 2013-03-10 10:15:37下载
- 积分：1
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SPI_DAC
使用VHDL语言实现了FPGA与DAC5688进行SPI通信更改寄存器值(The FPGA using VHDL language with the DAC5688 SPI communication to change the register value)
- 2011-10-23 21:14:45下载
- 积分：1
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track_version2
说明： fpga实现相关滤波算法中的CSK算法，采用仿真的方式验证结果
fpga是xilinx
仿真工具是vivado2018.2
语言是verilog(The CSK algorithm is implemented in FPGA, and the results are verified by simulation
FPGA is Xilinx
The simulation tool is vivado 2018.2
Language is Verilog)
- 2021-04-29 16:08:42下载
- 积分：1
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polar_encoder_1024 (1)
该部分的主要功能是完成基于FPGA的polar码编码。(The main function of this part is to complete the FPGA-based polar code coding.)
- 2021-01-10 16:58:50下载
- 积分：1
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FPGA2-DSP2-EDMA
例程是基于quartus的，FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)
- 2020-12-04 16:09:24下载
- 积分：1
