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作者:新舜唐日期:2008
--author: Suntion Tang
--date: 2008-6-7
-- two warning
--modify: By Suntion Tang at 2008-6-14
--description: 顶层文件,由于此系统简单,
-- 且底层文件不多,故放弃原理图描述,采用VHDL语言描述-author: Suntion Tang date: 2008-6-7 two warning modify: By Suntion Tang at 2008-6-14 description: the top-level documents, as a result of this system is simple, and not more than the bottom of a document, they give up the schematic description of the use of VHDL language description
- 2022-04-23 09:59:29下载
- 积分:1
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FPGA的专业综合工具,学习此第三方工具的经典教程
FPGA的专业综合工具,学习此第三方工具的经典教程-FPGA 专 业 酆 危 撸 学魏 说 叩 木坛
- 2022-05-24 03:46:54下载
- 积分:1
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adc0809
1、用状态机设计A/D转换器ADC0809的采样控制电路,并在数码管上显示转换结果;
2、设置有复位和启动/保持开关,要求
⑴ 复位开关用来使A/D转换器复位,并做好A/D转换准备;
⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果,即按一下启动/保持开关,启动A/D转换器开始转换,再按一下启/停开关,停止转换并保持结果。
3、采用Verilog HDL语言设计符合上述功能要求的控制电路。(1, with the state machine design A/D converter ADC0809 sampling control circuit and display the results on the digital conversion 2 is provided with a reset and start/hold switch, reset switch is used to make the request ⑴ A/D converter reset and do A/D conversion ready ⑵ start/hold switch is used to control the A/D converter starts converting or stop the conversion to maintain a continuous result that by clicking Start/hold switch, start the A/D converter to start the conversion, and then Click the start/stop switch stops the conversion and keep the results. 3, using Verilog HDL language designed to meet the functional requirements of the above-mentioned control circuit.)
- 2021-01-02 21:38:57下载
- 积分:1
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done, would not have introduced the document on the bar, IEEE1364 standard (open...
做EDA的,就不用介绍这个文件了吧,IEEE1364标准(开放)。-done, would not have introduced the document on the bar, IEEE1364 standard (open).
- 2022-03-25 09:59:57下载
- 积分:1
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- 2022-01-25 14:18:53下载
- 积分:1
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LCD1602
通过编写verilog语言完成数据的在液晶LCD1602显示(By writing verilog language to complete the data displayed on the LCD LCD1602)
- 2013-08-04 13:12:05下载
- 积分:1
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tcp_tiaoshi
fpga_sopc_enc28j60_tcp_ip_测试,源码程序包,本人测试通过!(Fpga_sopc_enc28j60_tcp_ip_ test, the source code packets, I test through!)
- 2012-03-05 11:26:19下载
- 积分:1
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err
在一些系统中,经常用到对触发信号延时一段时
间后,再对某些目标信号进行采集,通常这段延时要求
非常精确,还要做到范围可调,一般这种延时的最小时
间单位小于100ns。如果选用普通微控制器,延时系统的操作界面比较容易实现,但是靠软件延时得到结果的准确性较低。考虑到芯片功能、开发环境以及接口方便等问题,最终选用一片常用的AlteraSVCPLD
EPM7128SLC3411]作为系统的核心控制部分,来实现
信号延时、输人设定、运行显示的功能。应用Veril-
o苦2〕语言,在Altera的Quartus11WebEditio详3〕软件
环境下进行编程仿真,最后烧写芯片进行系统硬件测试
-err
- 2022-03-12 04:01:42下载
- 积分:1
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VHDL的初学者可以参考此VHDL加法器,相信会给你带来不小的收获...
VHDL的初学者可以参考此VHDL加法器,相信会给你带来不小的收获-VHDL beginner can refer to the VHDL adder, I believe will bring you not a small harvest
- 2022-05-20 03:51:48下载
- 积分:1
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222
说明: VHDL BISS,SSI,ENDAT2.2, ENCODER
- 2020-11-24 17:46:39下载
- 积分:1