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verilog写的数字频率计的选择模块,用与显示的选择
verilog写的数字频率计的选择模块,用与显示的选择-written in Verilog digital frequency meter option module, used and display options
- 2022-02-01 05:29:25下载
- 积分:1
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这是一个控制芯片CPLD 1394的verilog程序,可以参考应用。
这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.-This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.
- 2022-03-11 06:04:09下载
- 积分:1
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A simple sequential lights
A simple sequential lights
- 2022-08-17 06:37:02下载
- 积分:1
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LDPC码的编码和解码过程。有testbentch。
ldpc编解码程序。有testbentch。-ldpc encoding and decoding process. There testbentch.
- 2022-03-12 16:50:03下载
- 积分:1
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csbar(3) : X"E0000" to X"E01FF"
-- M68008 Address Decoder
-- Address decoder for the m68008
-- asbar must be 0 to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
-- download from www.pld.com.cn & www.fpga.com.cn
--- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn
- 2022-02-26 21:53:57下载
- 积分:1
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Lpfilter_20190503
说明: 环路滤波器是通信信号调制解调中最重要的一个部分,环路滤波器设计的好坏将直接影响到接收机的性能指标,二阶锁频辅助三阶锁相环路滤波器可以稳定跟踪具有加加速度的信号源,是现代通信中非常实用的技术,本文中详细编写了单载波信号产生模块、信道噪声模块、数字正交下变频模块、鉴频鉴相模块、环路滤波器模块,并包含了完整的testbench模块,对于初学者非常有用。(Loop filter is the most important part of communication signal modulation and demodulation. The design of loop filter will directly affect the performance index of receiver. The second-order frequency locking assisted third-order phase-locked loop filter can stably track the signal source with acceleration speed, which is a very practical technology in modern communication. In this paper, the single carrier signal generation module and channel noise are written in detail Sound module, digital orthogonal down conversion module, frequency and phase detection module, loop filter module, and contains a complete testbench module, which is very useful for beginners.)
- 2020-11-11 01:27:25下载
- 积分:1
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DCT_IDCT
DCT and Idct with vhdl and verilog
- 2017-11-22 17:15:12下载
- 积分:1
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CPLD
基于CPLD 的光电脉冲码盘
信号四倍频电路设计-CPLD-based electro-optical pulse encoder signals four multiplier circuit design
- 2022-08-10 19:02:11下载
- 积分:1
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AGC
The AGC is a smart programmable gain amplifier (PGA). The amplifier gain is adjusted based upon
the input signal level so that the output is at a specified Target Gain. The AGC can be configured to
be either a mono or stereo input / output component. For illustration purposes, the following
discussion will highlight the stereo configuration.
- 2017-12-01 17:26:59下载
- 积分:1
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60进制减法
相比较 代码效率高
可以进行级联
60进制减法
相比较 代码效率高
可以进行级联-60 compared to 229 subtraction efficient code can be concatenated
- 2022-01-25 18:25:04下载
- 积分:1