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A comparison reference value has sram IP core, on the SOPC interested people hav...
一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.
- 2022-05-18 11:22:45下载
- 积分：1
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fft1024
1024点fft verilog hdl(1024-point fft verilog hdl)
- 2020-09-08 20:28:02下载
- 积分：1
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DS1302
说明： 本代码是控制DS1302的VHDL代码，浅显易懂，方便修改，注意看data sheet，保证时钟和各个延迟满足要求即可(This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays)
- 2020-10-22 14:57:23下载
- 积分：1
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TW2867_ADV7171
FPGA TW2867输入到ADV7171显示实验(FPGA TW2867 input to the ADV7171 display experiment)
- 2021-03-19 15:19:19下载
- 积分：1
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7 digital display decoder design 7 Digital is pure combinational circuits, usual...
7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
- 2022-08-11 21:55:01下载
- 积分：1
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fpga vhdl
fpga测温的框图和源码 希望能帮到大家 没有测试 紧供参考-fpga vhdl
- 2022-07-20 06:55:34下载
- 积分：1
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AHBPAPB
AMBA总线的AHB+APB源程序，供初学者学习。(Verilog for AHB and APB)
- 2012-07-11 16:16:04下载
- 积分：1
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spi_ad
FPGA与DAC芯片的SPI接口驱动，实现串行数据的传输。(Realizing the communication between FPGA and DA chip)
- 2017-06-23 12:38:22下载
- 积分：1
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这是用verilog语言实现的1024点ff程序t
这是用verilog语言实现的1024点ff程序t-This is achieved using Verilog 1024 language ff procedures point t
- 2022-08-03 20:30:05下载
- 积分：1
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iic的代码，是工程文件来的，是XILINX的，来自开源的
iic的代码，是工程文件来的，是XILINX的，来自开源的-IIC
- 2023-01-11 10:05:04下载
- 积分：1
