▍1. 4X4键盘密码比较模块,可以查看密码6
4X4 KEYPAD 的密码比较模块,可以核对6位的密码-4x4 KEYPAD password comparison module, can check the password 6
4X4 KEYPAD 的密码比较模块,可以核对6位的密码-4x4 KEYPAD password comparison module, can check the password 6
用状态机实现密码锁State machine used to achieve code lock-State machine used to achieve code lock
verilog源码,可实现两位的加法器,在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through
《Verilog HDL 程序设计教程》8-"Verilog HDL Design Guide" 8
本代码介绍了使用VHDL开发FPGA的一般流程,最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL,在软件开发平台ISE上完成,可以在较高速时钟频率(100MHz)下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真,并完成了综合布局布线,最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add
测试人体视觉的反应时间,可以作为vhdl编程的练习之用,也可以更进一步的开发成为具有商业价值的产品,这里面只是能够实现测试人体视觉反应时间的基本功能的程序-Test of human visual reaction time, can be used as VHDL programming exercises used can also be further developed into products with commercial value, there is only able to realize the human visual reaction time test the basic functions of the procedures
crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,-CRC check, certified correct, you can download directly, there are deficiencies can correct me,
1024点FFT快速傅立叶变换,包含说明文档和VHDL源代码,16位输入/输出,带DMA功能,xilinx的ip-1024-point FFT fast Fourier transform, and includes documentation, VHDL source code, 16 input/output, with DMA function, the ip xilinx
OFDM系统中的相位跟踪模块(Phase_Tracking)的FPGA实现-Phase_Tracking in OFDM sysytems
基于sopc技术的数字均衡器带通滤波器及12864液晶显示-Sopc technology-based digital equalizer band-pass filter and liquid crystal display 12864
FPGA应用举例,非常适合初学者,高手莫下-FPGA application, for example, very suitable for beginners, experts, under Mo
使用 c languageit 的 16 点基 2 fft 代码将 16 点时间域序列转换为频率域
FM收音机的解码及控制器VHDL语言实现,Xilinx提供的.别谢我.-FM radio decoder and controller VHDL, Xilinx provide. I thank other.
用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.
Altera的CycloneIII Start Board,使用的PFGA是3C25,包括原理图和PCB,用Cadence Allegro打开-Altera
this program performs multiplexing and demultiplexing
使用LPM_ROM的实际的例子-Use of practical examples LPM_ROM
verilog中调用门级电路的实验程序,实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode
The code is used to interface PC monitor with Spartan 3E for the display. if you run the program on spartan 3 you would be able to see different test pattern on the monitor screen