▍1. ALU vhdl
此模块模拟alu(算术逻辑单元)和测试台,以验证其工作是否正确。
和picoblaze完全兼容的mcu ip core-And PicoBlaze fully compatible mcu ip core
NiosII_Exercises_Ver3,this niosII 3.o for cyclone
用FPGA 是先键盘的程序,is good for you -FPGA is the first keyboard to use the procedure, is good for you
内容1:哈尔滨工程大学信息与通信工程学院的课件-适合初学VHDL语言的人。内容2:VHDL语言详解的讲义。-1: Harbin Engineering University College of Information and Communication Engineering of software- suitable for novice VHDL language. Content 2: VHDL language of the notes explain.
高速双端口RAM的vhdl实现。包含仿真波形-High-speed dual-port RAM realize the VHDL. Contains the simulation waveform
these files are written in verilog but i am uploading in text format
用VHDL语言实现8-3线编码器,16-4线编码器-VHDL language used to achieve 8-3 line encoder ,16-4-wire encoder
数字钟的实现 FPGA上运行 VHDL编写-Digital clock running on the FPGA to achieve the preparation of VHDL
一个使用VHDL设计的具有强大功能的32位CPU,这个文件包含了与之配套的DDR控制器程序!-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
利用分频可以产生一系列脉冲,根据输入脉冲的不同决定你得到的一系列脉冲频率-The use of sub-band can produce a series of pulses, according to input pulse of different decisions you have a series of pulse frequency
可综合的vhdl设计特点.pdf-synthesizable VHDL design features. Pdf
一个以太网卡的硬件描述,可以参考进行设计网卡芯片。-an Ethernet card hardware description, reference card chip design.
扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现-Frequency-hopping communication QUARTUS7.0 expanded development environment in the VHDL source code and the achievement of the overall block diagram
四选一编程语言,可以自动生成四选一器件。-First elected four programming languages, you can automatically generate a four selected devices.
PCI的VHDL源码希望对大家有用!-PCI VHDL source hope useful for all!
基于VHDL语言的3级序列的产生,可以循环产生周期为7的m序列 -Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence
一个FPGA的AVR_Core 仅供测试~-AVR_Core an FPGA-only test ~