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ram2fifo
异步fifo实现,通过双口ram实现异步fifo(Asynchronous FIFO implementation, through dual port RAM to achieve asynchronous FIFO)
- 2018-09-21 09:25:35下载
- 积分:1
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VHDL example code
电路酒窖杂志的vhdl示例。vga控制器、视频发生器等PS2鼠标vhdl
- 2022-05-06 09:12:27下载
- 积分:1
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Verilog版的C51核(OC8051)
Verilog版的C51核(OC8051)-Verilog version of the C51 core (OC8051)
- 2022-04-30 06:36:25下载
- 积分:1
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mimaiic
基于AT89C51的密码锁(掉电可记忆密码)的程序(Based on AT89C51 lock (down to remembering passwords) program)
- 2013-06-06 11:38:13下载
- 积分:1
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8051core-Verilog
用verilog在FPGA内部实现8051内核,超好、超难找的资料!共享出来!(Verilog FPGA internal 8051 core, super, super hard to find! Shared out!)
- 2020-06-28 22:00:02下载
- 积分:1
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七人表决器
七人表决器,当有四人或四人以上的人同意是,表决通过。每个裁判控制一个开关,高电平表同意,在quartusII上用全加器来实现,当表决通过时,实验箱上的LED灯亮
- 2022-02-03 05:43:46下载
- 积分:1
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application-in-card-and-servo-drive
AB相编码器解码接口_PWM输出SOPC方案及其在运动控制卡和伺服驱动器中的应用(AB phase encoder decoder interface _PWM output SOPC program and its application in motion control card and servo drive)
- 2012-03-22 12:44:52下载
- 积分:1
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Block-cipher-lock
密码锁verilog源代码,包括四个七段数码管显示模块,设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)
- 2014-01-11 23:57:19下载
- 积分:1
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uart
说明: 串口通信通用模块,FPGA Verilog语言 ise,vivado环境(uart,FPGA Verilog, ise,vivado)
- 2020-06-22 07:20:01下载
- 积分:1
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interpolator
说明: 插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现(Interpolation filter, audio decoder for modulation and demodulation, filter coefficient shift combined with the realization of)
- 2008-10-21 12:49:38下载
- 积分:1