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SinGen
使用Verilog编写的正弦波生成工程,使用ROM核产生,利用mif文件(Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file)
- 2015-04-24 16:40:21下载
- 积分:1
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Timing_Closure
详细讲解时序约束培训教材,有利于更好对时序约束的理解(Timing constraints elaborate training materials, facilitate better understanding of the timing constraints)
- 2010-08-12 20:02:33下载
- 积分:1
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BCD-counter
一个2位的BCD码十进制加法计数器电路,输入为时钟信号CLK,进位
输入信号CIN,每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT,输入时钟信号CLK用固定时钟,进位输入信号CIN.
(A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output signal COUT, each BCD code decimal adder counter' s output signal, the input clock signal CLK Fixed clock, binary input signal CIN.)
- 2020-10-28 19:29:58下载
- 积分:1
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这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章,实用性很强的,在这里也感谢这篇文章的作着...
这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章,实用性很强的,在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was
- 2022-05-13 15:53:30下载
- 积分:1
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jiaotongdeng
交通灯通过数码管显示,几种模式可调,还可以时间可设,适合初学者入门参考学习。(LED traffic lights can be set to several modes adjustable time beginners reference ~ ~ ~)
- 2013-08-25 10:02:34下载
- 积分:1
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firhalfband
利用matlab提供的firhalfban函数设计阶数为16、通阻带容限为0.0001的半带滤波器。仿真测试滤波前后的信号时域图,回执滤波器的频率响应特性图(Provided firhalfban function using matlab design order of 16, through the 0.0001 stopband wool half-band filter. Simulation test filtered time domain signal before and after, receipt filter frequency response characteristic diagram)
- 2020-07-03 21:40:02下载
- 积分:1
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verilog
数字信号除了的FPGA实现的Verilog源代码,之前发过一份是VHDL,各有所需吧,需要的看看吧(Digital signal in addition to the realization of the FPGA Verilog source code, send before a is VHDL, each have need it, need to look at it
)
- 2012-02-25 15:06:35下载
- 积分:1
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fwwallace
wallace tree multiplier in verrilog
- 2013-03-19 00:15:07下载
- 积分:1
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波形产生器:用VHDL编写的波形产生器程序
波形产生器:用VHDL编写的波形产生器程序-Waveform Generator: Using VHDL prepared waveform generator procedure
- 2022-02-16 00:06:52下载
- 积分:1
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基于Verilog代码简单
simple code based on verilog
shifter , cla ,clg , ALU ,PC, decoder ,
tb_top
- 2022-02-26 06:52:19下载
- 积分:1