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FPGAdesignXilinx
华为内部资料，关于FPGA设计的详细过程介绍，很不错的。本文档从FPGA器件结构出发以速度路径延时大小和面积资源占用率为主题描述在FPGA设计过程中应当注意的问题和可以采用的设计技巧。(Huawei internal information, with regard to detailed FPGA design process of introduction, it is good. This document from the FPGA device structure in order to speed the path delay and area the size of the theme of the occupancy rate of resource description in the FPGA design process should pay attention to the problems and design techniques can be used.)
- 2020-12-21 13:59:08下载
- 积分：1
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cyclone and cyclone2 system used in the use 5v, making FPGA chip compatible with...
cyclone和cyclone2用在5v系统里使用方法,使得FPGA芯片在5V系统中兼容-cyclone and cyclone2 system used in the use 5v, making FPGA chip compatible with the 5V system
- 2022-02-03 17:24:31下载
- 积分：1
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Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-06-13 02:00:08下载
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dds
说明： 实现数字频率合成实验，加载数据ram,形成波形(The experiment of digital frequency synthesis is realized, and the data RAM is loaded to form the waveform)
- 2020-11-10 18:12:36下载
- 积分：1
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xilinx simulator programme of serial port
xilinx的串口仿真程序-xilinx simulator programme of serial port
- 2022-11-08 03:05:05下载
- 积分：1
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gold
基于vhdl语言的15位gold序列的设计的开端一部分程序(Vhdl language based on sequences of the 15 gold as part of the beginning of the design process)
- 2011-05-16 21:48:38下载
- 积分：1
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JSFP
奇数分频-此程序对输入频率sysclk有奇数（X）分频的功能(Odd frequency- this program has an odd number of input frequency sysclk (X) frequency function)
- 2011-08-01 12:37:42下载
- 积分：1
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使用vhdl语言实现对led的控制，还有电路仿真
使用vhdl语言实现对led的控制，还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation
- 2022-03-12 11:40:55下载
- 积分：1
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用verilog写的基于cpld的出租车计费器的源码，需要的参考一下
用verilog写的基于cpld的出租车计费器的源码，需要的参考一下-Use verilog to write a taxi based cpld billing device source code, need to refer to
- 2022-06-11 23:05:49下载
- 积分：1
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Verilog计数器、编码器、加法器
verilog编码器、计数器、加法器的程序(Verilog encoder, counter, adder procedures)
- 2019-01-26 21:50:01下载
- 积分：1
