-
FPGA DDS
说明: 使用DE2实现DDS,步骤简单,配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)
- 2020-06-23 10:00:01下载
- 积分:1
-
HDMI_FPGA
该源码可基于FPGA设置多分辨率的HDMI显示,且其包含了完整的时序和端口、地址映射,可以很方便的将其移植(The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted)
- 2020-12-17 11:09:12下载
- 积分:1
-
vhdl设计事例,有助于FPGA初学着,High
vhdl设计事例,有助于FPGA初学着,High-Performance 1024-Point
Complex FFT-vhdl design examples, to help novice FPGA. High-Performance 1024-Point Complex FFT
- 2023-06-12 19:40:12下载
- 积分:1
-
ozgul2013
Digital pre-distortion (DPD) is an advanced digital
signal-processing technique that mitigates the effects of power
amplifier (PA) nonlinearity in wireless transmitters. DPD plays
a key role in providing efficient radio digital front-end (DFE)
solutions for 3G/4G basestations and beyond. Modern FPGAs
are a promising target platform for the implementation of flexible
wireless DFE solutions, including DPD.
- 2019-01-05 18:20:30下载
- 积分:1
-
硬件描述语言
verilog HDL 4×4矩阵键盘驱动程序包括硬件电路图-verilog
- 2022-04-27 04:55:21下载
- 积分:1
-
Endat2_1_freq
用verilog实现endat2_1驱动,并用signalTap捕捉信号。(Using verilog achieve endat2_1 drive and use signalTap capture signal.)
- 2021-04-26 15:08:45下载
- 积分:1
-
基于FPGA的数字钟
1.设计一个具有24进制计时、显示、整点报时、时间设置和闹钟功能的数字钟,要求时钟的最小分辨率时间为1s。2.多功能数字钟系统功能的具体描述如下: 计时:正常工作状态下,每日按24小时计时制计时并显示,蜂鸣器逢整点报时。 校时: 请点击左侧文件开始预览 !预览只提供20%的代码片段,完整代码需下载后查看 加载中 侵权举报
- 2022-05-23 08:48:32下载
- 积分:1
-
uart vhdl代码
用于uart 的通信的vhdl代码,可以直接使用
- 2022-07-27 17:23:12下载
- 积分:1
-
VHDL与Verilog的比较
VHDL与Verilog的比较-VHDL and Verilog comparison
- 2022-04-14 10:03:59下载
- 积分:1
-
基于无源蜂鸣器和矩阵按键的电子琴系统设计
基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)
- 2020-06-21 01:20:08下载
- 积分:1