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I2C_ise9migration
说明： IIC 的Verilog实现，工程是在Xilinx的ISE9.1上实现的(IIC of the Verilog implementation project was implemented on Xilinx' s ISE9.1)
- 2010-04-02 09:26:54下载
- 积分：1
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一个FPGA的AVR_Core
仅供测试~
一个FPGA的AVR_Core
仅供测试~-AVR_Core an FPGA-only test ~
- 2023-08-16 08:25:03下载
- 积分：1
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lehmer_rng
lehmer random number generator method to generate test patterns of circuit
- 2015-01-23 15:22:09下载
- 积分：1
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huffman
huffman transform in vhdl language
- 2013-08-26 13:17:15下载
- 积分：1
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Several Example FPGA design contest
几个fpga竞赛的设计例-Several Example FPGA design contest
- 2022-09-16 03:50:03下载
- 积分：1
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以太网总线源代码，里面有详细的文档说明，已经过FPGA验证。...
以太网总线源代码，里面有详细的文档说明，已经过FPGA验证。-Ethernet bus source code, which has a detailed document that has been FPGA verification.
- 2023-08-25 00:30:05下载
- 积分：1
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Modelsim 5.6 se 简易使用教程
Modelsim 5.6 se 简易使用教程 -Modelsim 5.6 se easy to use tutorial
- 2023-03-01 14:15:03下载
- 积分：1
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CPU
运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)
- 2020-09-21 10:37:53下载
- 积分：1
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test_ad9852
使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。使用的DDS芯片为AD9852，在QuartusII下编写。(Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.)
- 2010-01-27 17:02:16下载
- 积分：1
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ADC VHDL 代码
使用VHDI Dispaly字符。显示了一个模拟的正常工作的LCD控制器硬件实现。这种模拟演示了不同的状态机协同工作的方式。作为初始化序列完成时，主状态机的命令的状态开始。
- 2022-02-24 19:19:54下载
- 积分：1
