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EX7_BINARY2GRAY
本模块是实现格雷码和二进制码的转换，并给出仿真测试文件(This module is to achieve the conversion of Gray code and binary code, and give the simulation test file)
- 2015-04-14 16:48:38下载
- 积分：1
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Hilbert
说明： 基于altera fpga的fir IP核实现希尔伯特变换，有matlab仿真(Based on Altera FPGA fir IP core to achieve Hilbert transform, matlab simulation)
- 2020-10-05 11:27:38下载
- 积分：1
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8 位修改 Booth 型乘法器
这是基数 4 修改 Booth 型乘法器为 8 位。它可以用于任何大小的操作数的乘法......
- 2022-01-24 13:25:05下载
- 积分：1
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verilog user guide
verilog语法说明，包含verilog golden reference guide，verilog 2001语法(verilog golden reference guide)
- 2018-05-08 22:50:16下载
- 积分：1
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ALTERA关于CCD的一些verilog程序，都通过运行无误的。
ALTERA关于CCD的一些verilog程序，都通过运行无误的。-ALTERA on a number of Verilog CCD procedures, both by running unmistakable.
- 2022-06-17 09:45:06下载
- 积分：1
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PERI4-DM9000A
基于FPGA的DM9000A芯片的网络数据采集系统，基于NIOS架构，c语言编程，资料齐全，包含不止5个源程序，绝对受用！(FPGA-based the DM9000A chip network data acquisition system based on NIOS architecture, c programming language, the information is complete, contains more than 5 source code is absolutely good enough!)
- 2020-09-16 16:57:55下载
- 积分：1
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integrator
this code for integrator for 8 bit signal
- 2010-01-07 16:06:04下载
- 积分：1
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it performs the serail dividing operations
it performs the serail dividing operations
- 2022-11-07 21:55:03下载
- 积分：1
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基于DDS的DA正弦波输出
Sample behavioral waveforms for design file sin_rom.vThe following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design sin_rom.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 3F0, 3F1, 3F2, 3F3, ...). The design sin_rom.v has one read port. The read port has 1024 words of 10 bits each. The output of the read port is unregistered. Fig. 1 : Wave showing read operation. The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until
- 2022-01-26 04:06:16下载
- 积分：1
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altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。...
altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。-altera
- 2022-03-05 12:43:51下载
- 积分：1
