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使用Xilinx3S400开发的钢板检测算法中心化算法，通过测试。(a vhdl-program use Xilinx3S400)
- 2009-04-12 22:09:45下载
- 积分：1
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counter
设计一个十进制计数器模块，输入端口包括 reset、up_enable 和 clk，输出端口为 count
和 bcd，当 reset 有效时（低电平），bcd 和 count 输出清零，当 up_enable 有效时（高电
平），计数模块开始计数（clk 脉冲数），bcd 为计数输出，当计数为 9 时，count 输出一
个脉冲（一个 clk周期的高电平，时间上与“bcd=9”时对齐）(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9" when aligned))
- 2013-04-13 19:53:29下载
- 积分：1
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基于fpga和xinlinx ise的usb端口vhdl程序，希望对你有所帮助！
基于fpga和xinlinx ise的usb端口vhdl程序，希望对你有所帮助！-VHDL program for USB port based fpga and xinlinx ise, wish help for you!
- 2022-02-05 00:39:46下载
- 积分：1
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希尔伯特变换是通信系统中的一个重要组成部分，如：
The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented.
The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940).
The design is fully pipelined for maximum throughput.
- 2023-02-02 09:20:04下载
- 积分：1
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alpha-beta
阿尔法贝塔滤波器，是卡曼滤波器的简化，比卡曼滤波器速度快。这是一个实例。(aplha-beta filter is filter that faster than kalman filter)
- 2020-11-25 20:09:31下载
- 积分：1
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Altera官方FPGA电机控制的中文文档
Altera官方FPGA电机控制的中文文档，很不错的参考资料(Altera Official FPGA Motor Control Chinese Document, Good Reference)
- 2021-03-18 13:49:19下载
- 积分：1
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Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP...
Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)-Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP)
- 2022-02-12 19:56:59下载
- 积分：1
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SPI的verilog代码的可编程时钟
SPI Verilog code with programmable clock
- 2022-10-30 18:55:03下载
- 积分：1
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led
控制8个发光二极管中的一个发光二极管发光，其它7个发光二极管都出于截止状态，发光二极管的导通顺序按照向左或向右两个方向移动，并且通过按键控制发光二极管循环发光移动的方向。(Control of a light-emitting diode light-emitting eight light-emitting diodes, the other seven light-emitting diodes for the cut-off state, light-emitting diode conduction order in accordance with the left or right move in both directions, and light-emitting diode cycle luminous button control mobile direction.)
- 2012-11-09 12:33:57下载
- 积分：1
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vhdl code for multiplexer and detemines how multiplexer works
vhdl code for multiplexer and detemines how multiplexer works
- 2022-02-21 06:20:43下载
- 积分：1
