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SoC_WishboneSystem
SoC-Wishbone System IP核的VHDL语言源代码,需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)
- 2008-01-03 11:14:59下载
- 积分:1
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VLSI implementation of high speed and high resolution FFT algorithm based on Rad...
VLSI implementation of high speed and high resolution FFT algorithm based on Radix 2 for DSP application
- 2022-05-07 09:52:02下载
- 积分:1
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Farrow-filter-design
两篇中文论文,详细叙述了Farrow滤波器的设计方式和理论基础,非常实用!(Two Chinese papers, described in detail Farrow filter design methods and theoretical foundation, very useful!)
- 2013-11-15 17:15:20下载
- 积分:1
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寄存器的VHDL源码.可能有点简单 新手大家间量 希望和大家学习...
寄存器的VHDL源码.可能有点简单 新手大家间量 希望和大家学习-VHDL source register. May be a bit simple volume between novice you would like to learn
- 2022-12-21 02:40:03下载
- 积分:1
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VHDL与Verilog的比较
VHDL与Verilog的比较-VHDL and Verilog comparison
- 2022-04-14 10:03:59下载
- 积分:1
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urisc
自己用verilog编写的urisc程序,调试成功,压缩包里有仿真图像,值得学习参考。(Written in verilog urisc program debugging, simulation image compression bag, worth learning reference.)
- 2021-04-22 17:38:48下载
- 积分:1
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vendingmachine
vendingmachine vhdl code
- 2011-12-03 20:53:39下载
- 积分:1
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Hamming
汉明码转换,在FPGA上用verilog实现(hamming encoder, using FPGA)
- 2011-05-22 09:46:09下载
- 积分:1
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sopcAD7352nios
基于sopc的7352的ad模块的nios软核多通道编写,verilog 写的(The sopc 7352 AD module nios soft core multichannel write. Rar
)
- 2012-11-03 21:37:42下载
- 积分:1
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DDR2_XILINX
xilinx FPGA设计需要的DDR2文件,可以应用于实际设计中(xilinx FPGA design needs DDR2 files that can be applied to the actual design)
- 2014-10-09 09:54:05下载
- 积分:1