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infrared_receive
红外接收处理，根据外部波形记录波形的高低电平时间，从而得到波形数据。(Infrared receiver processing, according to the external waveform waveform record high and low times, resulting waveform data.)
- 2013-09-27 11:09:02下载
- 积分：1
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shizhong
VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)
- 2014-01-09 18:29:40下载
- 积分：1
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stm32-and-fpga-communication-by-spi
该实验完成的功能是STM32与FPGA通信(The function of the experiment is STM32 and FPGA communication)
- 2020-11-16 09:29:42下载
- 积分：1
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用verilog写的cpld的各种分频程序，希望大家指正，谢谢！
用verilog写的cpld的各种分频程序，希望大家指正，谢谢！-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!
- 2023-01-20 06:35:04下载
- 积分：1
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96x96数字复用/解复用SPI
96x96 Digital MUX/DEMUX via SPI
- 2023-08-24 02:45:04下载
- 积分：1
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gold
基于vhdl语言的15位gold序列的设计的开端一部分程序(Vhdl language based on sequences of the 15 gold as part of the beginning of the design process)
- 2011-05-16 21:48:38下载
- 积分：1
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cpld/fpga Integral comb filter (CIC) design
cpld/fpga积分梳状滤波器(CIC)设计-cpld/fpga Integral comb filter (CIC) design
- 2022-07-08 17:49:24下载
- 积分：1
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SCAN_LED
基于EDA技术中的对LED扫描电路的实验，程序能成功运行，能直接在开发板上看实验结果(EDA-based LED technology to scan the experimental circuit, the program can run successfully, can see directly in the development of on-board results)
- 2009-06-05 11:49:53下载
- 积分：1
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Altera公司的NIOSⅡ处理器，VHDL语言编译，然后在C语言下的nios……
ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
- 2022-03-21 08:10:03下载
- 积分：1
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基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现...
基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现
-FPGA-based design of traffic lights have Verilog HDL source code, simulation map with pin configuration map has been downloaded realize
- 2022-06-27 19:08:32下载
- 积分：1
