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C4gx15_starter_qsys_pcie_gen1x1
PCIe demo sample code
- 2020-12-09 16:39:19下载
- 积分：1
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VHDL_programs
VHDL programmes for basic digital circuits. begineers can learn easily
- 2013-09-28 13:46:58下载
- 积分：1
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电梯
利用verilog编写的电梯程序，实现基本的电梯运行功能(Elevator program written by Verilog)
- 2018-11-25 11:39:50下载
- 积分：1
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Radix-8 Booth Encoded Modulo
vhdl 代码为基数 8 展位编码模块乘数与自适应延迟的高动态范围残留一些系统
- 2022-08-25 03:41:29下载
- 积分：1
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UG586-7SeriesDMIUserGuide
UG586 - Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )(UG586- Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB ))
- 2015-02-05 20:02:21下载
- 积分：1
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modelsim_example_c
modelsim仿真，大量vhdl程序，验证，很有价值！(The ModelSim Simulation, a large number of VHDL procedures, validation, great value!)
- 2013-05-05 15:11:06下载
- 积分：1
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高级加密标准AES的FPGA实现，支持128，256密钥长度格式
高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
- 2022-03-25 02:47:08下载
- 积分：1
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sdram-control-verilog
SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.)
- 2009-12-11 15:01:46下载
- 积分：1
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endat
endat 2.2 接口内核，发送命令至编码器或从编码器接收位置值(endat 2.2 interface cores, sending commands to the encoder or received the encoder position values)
- 2021-05-12 18:30:02下载
- 积分：1
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iq_balance
调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)
- 2021-04-23 17:48:47下载
- 积分：1
