mig_7series_v1_9

代码说明：

  DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。(DDR3 Controller，complete DDR3 controll，have pass verificaion.)

文件列表：

mig_7series_v1_9
................\datasheet.txt,2607,2016-08-01
................\docs
................\....\phy_only_support_readme.txt,608,2016-08-01
................\....\ug586_7Series_MIS.pdf,79723,2013-03-27
................\example_design
................\..............\log.txt,5089,2016-08-01
................\..............\par
................\..............\...\create_ise.bat,3137,2016-08-01
................\..............\...\ddr_icon_cg.xco,1411,2016-08-01
................\..............\...\ddr_ila_basic_cg.xco,3896,2016-08-01
................\..............\...\ddr_ila_rdpath_cg.xco,3898,2016-08-01
................\..............\...\ddr_ila_wrpath_cg.xco,3897,2016-08-01
................\..............\...\ddr_vio_async_in_sync_out_cg.xco,1617,2016-08-01
................\..............\...\ddr_vio_sync_async_out72_cg.xco,1614,2016-08-01
................\..............\...\example_top.cpj,757534,2016-08-01
................\..............\...\example_top.ucf,30139,2016-08-01
................\..............\...\example_top.xdc,39577,2016-08-01
................\..............\...\ise_flow.bat,4598,2016-08-01
................\..............\...\makeproj.bat,3137,2016-08-01
................\..............\...\readme.txt,4232,2016-08-01
................\..............\...\rem_files.bat,12849,2016-08-01
................\..............\...\rem_files.tcl,8287,2016-08-01
................\..............\...\set_ise_prop.tcl,6976,2016-08-01
................\..............\...\xst_options.txt,192,2016-08-01
................\..............\rtl
................\..............\...\example_top.v,59182,2016-08-01
................\..............\...\traffic_gen
................\..............\...\...........\mig_7series_v1_9_axi4_tg.v,18531,2013-03-27
................\..............\...\...........\mig_7series_v1_9_axi4_wrapper.v,33339,2013-03-27
................\..............\...\...........\mig_7series_v1_9_cmd_prbs_gen_axi.v,10316,2013-03-27
................\..............\...\...........\mig_7series_v1_9_data_gen_chk.v,7120,2013-03-27
................\..............\...\...........\mig_7series_v1_9_tg.v,25672,2013-03-27
................\..............\sim
................\..............\...\ddr3_model.v,152506,2016-08-01
................\..............\...\ddr3_model_parameters.vh,235718,2016-08-01
................\..............\...\isim_files.prj,10154,2016-08-01
................\..............\...\isim_options.tcl,3232,2016-08-01
................\..............\...\isim_run.bat,3300,2016-08-01
................\..............\...\readme.txt,7435,2016-08-01
................\..............\...\sim.do,6106,2016-08-02
................\..............\...\sim.do.bak,6093,2016-08-02
................\..............\...\sim_tb_top.v,50005,2016-08-02
................\..............\...\sim_tb_top.v.bak,49948,2016-08-01
................\..............\...\vsim.wlf,14065664,2016-08-03
................\..............\...\wave.do,5065,2016-08-02
................\..............\...\wiredly.v,5452,2016-08-01
................\..............\...\wlft5bhzcw,21839872,2016-08-15
................\..............\...\wlftr0h9h9,17276928,2016-08-11
................\..............\...\wlftxzzt3d,14475264,2016-08-05
................\..............\...\work
................\..............\...\....\htm" target=_blank>_info,37731,2016-08-15
................\..............\...\....\_lib.qdb,98304,2016-08-15
................\..............\...\....\_lib1_2.qdb,180224,2016-08-15
................\..............\...\....\_lib1_2.qpg,39501824,2016-08-15
................\..............\...\....\_lib1_2.qtl,1571878,2016-08-15
................\..............\...\....\_vmake,29,2016-08-15
................\..............\...\xsim_files.prj,10146,2016-08-01
................\..............\...\xsim_options.tcl,3193,2016-08-01
................\..............\...\xsim_run.bat,3325,2016-08-01
................\..............\synth
................\..............\.....\example_top.lso,6,2016-08-01
................\..............\.....\example_top.prj,6656,2016-08-01
................\..............\.....\synplify_pro.tcl,7955,2016-08-01
................\mig.prj,18722,2016-08-01
................\mig_7series_v1_9.csv,5187,2016-08-01
................\user_design
................\...........\constraints
................\...........\...........\mig_7series_v1_9.ucf,30138,2016-08-01
................\...........\...........\mig_7series_v1_9.xdc,39544,2016-08-01
................\...........\log.txt,13716,2016-08-01
................\...........\rtl
................\...........\...\axi
................\...........\...\...\mig_7series_v1_9_axi_ctrl_addr_decode.v,6853,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_ctrl_read.v,6159,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_ctrl_reg.v,6113,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_ctrl_reg_bank.v,29008,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_ctrl_top.v,28756,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_ctrl_write.v,7619,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc.v,48930,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc_ar_channel.v,9470,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc_aw_channel.v,10328,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc_b_channel.v,7797,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc_cmd_arbiter.v,13143,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc_cmd_fsm.v,12014,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc_cmd_translator.v,10449,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc_incr_cmd.v,10575,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc_r_channel.v,13318,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc_simple_fifo.v,5530,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc_wrap_cmd.v,15909,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc_wr_cmd_fsm.v,12015,2016-08-01
................\...........\...\...\mig_7series_v1_9_axi_mc_w_channel.v,17599,2016-08-01
................\...........\...\...\mig_7series_v1_9_ddr_axic_register_slice.v,19126,2016-08-01
................\...........\...\...\mig_7series_v1_9_ddr_axi_register_slice.v,22579,2016-08-01
................\...........\...\...\mig_7series_v1_9_ddr_axi_upsizer.v,44079,2016-08-01
................\...........\...\...\mig_7series_v1_9_ddr_a_upsizer.v,49824,2016-08-01
................\...........\...\...\mig_7series_v1_9_ddr_carry_and.v,4266,2016-08-01
................\...........\...\...\mig_7series_v1_9_ddr_carry_latch_and.v,4310,2016-08-01
................\...........\...\...\mig_7series_v1_9_ddr_carry_latch_or.v,4250,2016-08-01
................\...........\...\...\mig_7series_v1_9_ddr_carry_or.v,4319,2016-08-01