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基于Xilinx fpga的ddr2 控制器设计方法
基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
- 2022-08-11 18:36:22下载
- 积分：1
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qianzhaowang
一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP，实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)
- 2019-01-21 17:18:13下载
- 积分：1
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Cadence VHDL Operational the package, seeking to achieve root, You are not squar...
Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
- 2022-08-16 03:35:39下载
- 积分：1
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design through verilog hdl
design through verilog hdl
- 2023-04-07 06:25:04下载
- 积分：1
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即使
偶数分频，包括验证程序，verilog实现，可综合-Even-numbered sub-frequency, including the verification process, verilog realize, can be integrated
- 2022-04-22 19:15:58下载
- 积分：1
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FDDDDRSDRAMP
一种基于FPGA 实现DDDR SDRAM的控制器
(DDDR SDRAM controller based on FPGA)
- 2012-08-29 23:52:53下载
- 积分：1
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M-ary-QAM-in
研究信道噪声对M-ary QAM的影响，适合数字通讯从业者(Effect of channel noise on M-ary QAM in)
- 2015-07-15 09:45:41下载
- 积分：1
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verilogexample
verilog学习资料。附带简单的源代码列子，可以直接使用和仿真。(verilog learning materials. Source code with a simple Lie Zi, and simulation can be used directly.)
- 2011-05-26 11:53:24下载
- 积分：1
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bldc_motor_control_design_example
无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA( actel VERILOG BLDC control of the use of actel FPGA)
- 2020-10-29 09:19:57下载
- 积分：1
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本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考....
本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
- 2022-06-29 06:12:54下载
- 积分：1
