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uart
用veriolg 语言编写的串口通讯程序,通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )
- 2010-08-16 10:41:03下载
- 积分:1
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一个可以使用的RocketI/O开发实例。基于Xilinx FPGA Virtex5平台。
一个可以使用的RocketI/O开发实例。基于Xilinx FPGA Virtex5平台。-One can use RocketI/O development example. Based on Xilinx FPGA Virtex5 platform.
- 2022-02-12 14:18:54下载
- 积分:1
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基于无源蜂鸣器和矩阵按键的电子琴系统设计
基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)
- 2020-06-21 01:20:08下载
- 积分:1
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4X4键盘密码比较模块,可以查看密码6
4X4 KEYPAD 的密码比较模块,可以核对6位的密码-4x4 KEYPAD password comparison module, can check the password 6
- 2022-10-12 19:30:03下载
- 积分:1
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verilog
关于USB开发的verilog开发程序,非常的全面,学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)
- 2013-12-26 18:29:35下载
- 积分:1
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my_kmp_matching
说明: KMP算法的Verilog HDL实现,模式串从模块的外部输入,计算next函数,然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。(Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment for the Quartus II 8.0 Web Edition.)
- 2011-03-14 09:28:01下载
- 积分:1
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EPM570
非常好的EPM570(CPLD)学习程序源码,适合初学者,能让其快速入门(Very good EPM570 (CPLD) learning program source code, suitable for beginners, allowing its Quick Start)
- 2013-09-11 10:18:59下载
- 积分:1
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这些是Verilog文件但我上传文本格式(记事本)
these are verilog files but i am uploading in text(notepad) format
- 2022-12-19 09:00:04下载
- 积分:1
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vhdl,序列信号检测模块,此模块检测1110010,可改为任意序列,输出电位为1为检测出,否则为0...
vhdl,序列信号检测模块,此模块检测1110010,可改为任意序列,输出电位为1为检测出,否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0
- 2022-10-12 22:25:03下载
- 积分:1
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ADC_pf89
本verilog代码通过IIC总线实现了对 PCF8591AD、DA转换芯片的控制。适用于FPGA,亲测可用。(this is used for FPGA to control PCF8591(AD/DA) chip by verilog.)
- 2020-11-28 13:09:30下载
- 积分:1