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FPGAPDSCDMA
上海交大关于基于FPGA的DSCDMA的实现的毕业设计(Shanghai Jiaotong University based the FPGA DSCDMA, achieve graduation design)
- 2013-02-10 14:31:46下载
- 积分:1
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wm8731
wm8731的使用,用于音频信号的采集或者产生(wm8731 use for audio signal acquisition or produce)
- 2009-07-20 15:51:33下载
- 积分:1
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BRAT
early branch rename table(store rename table once the branch instruction comes in. Used in out of order pipeline processor)
- 2012-03-27 15:15:08下载
- 积分:1
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RS(255,247)编码解码器Verilog源代码
说明: RS(255,247)编码解码器Verilog源代码(Verilog source code of RS (255247) codec)
- 2021-02-08 17:09:54下载
- 积分:1
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Writing Testbenches using System Verilog
Material to learn how to use system verilog and how to write testbenches for verification.
- 2018-02-09 17:24:25下载
- 积分:1
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udp
说明: 网口UDP的FPGA仿真代码,经过测试能够实现预想功能(etherneit udp verilog fpga code)
- 2020-05-26 21:55:04下载
- 积分:1
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Verilog版的C51核(DW8051)
Verilog版的C51核(DW8051)-Verilog version of the C51 core (DW8051)
- 2022-02-27 07:41:54下载
- 积分:1
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game
反应速度测试小游戏,最小外设cpld游戏,带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)
- 2010-05-14 18:42:57下载
- 积分:1
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fffffff
如上图所示, Rst是低电平有效的系统复位信号,Clk是时钟信号。AB[5:0]是地址信号,DB[7:0]是数据信号,wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后,可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后,给出一个Clk周期宽度的脉冲信号start,则系统从存储器0地址处开始读出数据,读出的8位数据从低位开始以3位为一组,每个时钟周期输出一组,即第一个时钟周期输出[2:0]位,第二个时钟周期输出[5:3]位,第三个周期输出1地址的[0]位和0地址的[7:6]位,直至将存储器中64x8数据全部输出。若最后一组不足三位,则高位补0。
(As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2020-11-04 20:39:51下载
- 积分:1
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viterbi_soft
维特比译码器,调用IP核,软判决输入,开发平台Xilinx Spartan-6系列FPGA(viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA)
- 2021-01-17 22:58:46下载
- 积分:1