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processor
processor design istruction load pipeline ,hazard
- 2010-04-02 03:52:08下载
- 积分：1
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problem
在学习verilog 中与遇到一些列问题的整理。(this Documentation is about the problem about verilog which is meeted when i was learn FPGA)
- 2014-03-07 22:24:19下载
- 积分：1
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fpga
pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)
- 2020-12-08 20:39:20下载
- 积分：1
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jtag
verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)
- 2021-04-27 14:38:44下载
- 积分：1
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and VHDL source code
VHDL与源代码包-and VHDL source code
- 2022-07-21 05:42:10下载
- 积分：1
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实现LMS的VHDL代码。
Implement LMS vhdl code.
- 2022-07-11 07:46:06下载
- 积分：1
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N-bits-by-M-bits
这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)
- 2013-10-05 19:44:52下载
- 积分：1
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vhdl code for counterand detemines how counter
works
vhdl code for counterand detemines how counter
works
- 2023-03-20 20:40:03下载
- 积分：1
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exercise3
用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分：1
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用VHDL编写的计算器，能实现简单的加减乘除四则运算
用VHDL编写的计算器，能实现简单的加减乘除四则运算
- 2022-03-18 17:26:25下载
- 积分：1
