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turbo_encoder
在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)
- 2021-04-19 09:38:51下载
- 积分：1
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超大规模集成电路的VHDL基本编码…………
- 2022-03-26 19:32:17下载
- 积分：1
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本源码详细介绍了UART的经典实例，敬请下载，谢谢适用
本源码详细介绍了UART的经典实例，敬请下载，谢谢适用-The source described in detail a classic example of UART, please download, Thank you apply
- 2022-03-22 20:09:19下载
- 积分：1
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Radar-on-FPGA
主要论述了基于FPGA的末制导雷达伺服系统设计。结合末制导雷达讨论其电机控制、二阶伺服系统性能和PID校正算法,利用VHDL语言设计,实现基于FPGA的方位步进电机开环定位控制和俯仰直流电机闭环速度控制的伺服系统。结合实际应用中遇到的问题,提出了基于"反馈控制"理论的有效的补偿算法,该算法提高了伺服系统的稳定性、快速性和精度。(Mainly discusses the design of terminal guidance radar servo system based on Field Programmable Gates Array(FPGA).It includes the system’s electric machine control,second-order servo system performance and PID correction algorithm based on Virtual Hardware Description Language(VHDL) on azimuth stepping motor open loop positioning control and pitch direct current electric machine closed loop speed control of the FPGA servo system.In allusion to some factual problems during its application,presents corresponding effective solutions based on traditional control theory "Feedback Control".The fact proves that these methods can greatly improve the stability,speediness and precision of the original servo system.Additionally,a basic algorithm which can be realized in a terminal guidance radar servo system is given)
- 2012-08-11 17:51:55下载
- 积分：1
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ldpc
低密度校验码 ，很好用的代码，功能已经实现编码和译码(fpga ldpc)
- 2014-04-09 10:24:51下载
- 积分：1
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Code-Verilog
this is code verilog
- 2012-05-09 22:02:56下载
- 积分：1
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Interleaver_Deinterleaver
通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。(Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.)
- 2021-04-17 15:18:53下载
- 积分：1
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Chebyshev-filter
利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance.
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- 2013-09-05 20:04:36下载
- 积分：1
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VHDL编写的数字钟，在Q
VHDL编写的数字钟，在Q-ii下编译，实现闹铃设置与定时闹铃，分时秒显示-VHDL prepared digital clock, in the Q-ii under the compiler to achieve regular alarm and alarm settings, time-seconds display
- 2022-12-10 02:20:03下载
- 积分：1
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QPSK_DDS
说明： Implementing QPSK using DSS
- 2020-01-14 06:00:57下载
- 积分：1
