Interleaver_Deinterleaver

代码说明：

  通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。(Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.)

文件列表：

Interleaver_Deinterleaver
.........................\resource
.........................\........\Convolutional_Deinterleaver.v,10084,2011-07-08
.........................\........\Convolutional_Interleaver.v,9764,2011-07-08
.........................\........\deinterleaver_channel_cont.v,1180,2007-08-29
.........................\........\double_port_ram.v,888,2007-08-28
.........................\........\interleaver_channel_cont.v,1110,2007-08-29
.........................\........\Interleaver_Deinterleaver.v,3019,2011-07-08
.........................\........\Interleaver_Deinterleaver_Testbench.v,2873,2011-07-08
.........................\........\readme.txt,591,2016-01-21