登录
首页 » VHDL » 实现了三种乘法器,可以进行性能比较,比较有较之

实现了三种乘法器,可以进行性能比较,比较有较之

于 2022-08-06 发布 文件大小:22.46 kB
0 57
下载积分: 2 下载次数: 1

代码说明:

实现了三种乘法器,可以进行性能比较,比较有较之-multi

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • alu
    说明:  Verilog code for implementing simple ALU.
    2019-09-25 19:40:09下载
    积分:1
  • lcd_system
    LCD显示工程,其中包含了顶层文件和各个底层文件(LCD display project, which contains the top-level document and all underlying file)
    2013-07-24 08:58:53下载
    积分:1
  • VHDL for the hardware interface on the 8237 programming, you can carrying out fp...
    关于vhdl对硬件接口8237的编程,可以在进行fpga/cpld设计是作为模块用到-VHDL for the hardware interface on the 8237 programming, you can carrying out fpga/cpld design is used as a module
    2023-02-20 14:55:04下载
    积分:1
  • Idddc_30mF
    中频70M,30M带宽LFM信号,采样率为102.4M,,数字下变频后,还进行了三倍抽取,最后还得到I,Q两路信号 (IF 70M, 30M bandwidth LFM signal, the sampling rate 102.4M, under digital variable frequency after also carried out three times extracted, and finally also received the I and Q signals)
    2012-07-25 23:56:30下载
    积分:1
  • inv_matrix
    矩阵求逆模块硬件实现,用verilog语言,基于ISE开发环境(implement of inverse matrix)
    2021-03-24 10:19:14下载
    积分:1
  • ds1302_seg7
    使用Verilog完成DS1302的驱动,工程已经经过测试,可直接使用。(DS1302 using Verilog complete drive, the project has been tested and can be used directly.)
    2014-12-10 15:27:48下载
    积分:1
  • 11 阶FIR 数字滤波器,verolog描述,通过modelsim 6.0 仿真,Quartue综合...
    11 阶FIR 数字滤波器,verolog描述,通过modelsim 6.0 仿真,Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated
    2022-10-31 17:45:02下载
    积分:1
  • cfg9230
    ad9230的配置程序,差分输入输出,verilog(ad9230 configuration program, verilog)
    2021-03-18 19:09:19下载
    积分:1
  • LMS算法FPGA仿真
    自适应滤波器算法LMS ,的FPGA实现,采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)
    2020-06-24 01:00:02下载
    积分:1
  • ps2interface
    one of example about hardware design language
    2009-12-25 07:17:18下载
    积分:1
  • 696518资源总数
  • 104225会员总数
  • 32今日下载