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dds32_1
说明： 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)
- 2011-04-14 13:45:22下载
- 积分：1
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TIMING LEARNING
TIMING LEARNING -TIMING LEARNING
- 2023-04-26 09:15:03下载
- 积分：1
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这是个vhdl编写的16bit的加减法器
这是个vhdl编写的16bit的加减法器-This is vhdl prepared by the modified instruments used in the 16bit
- 2022-02-15 07:17:54下载
- 积分：1
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用VHDL实现视频控制程序(实现对图像的采集和压缩)
用VHDL实现视频控制程序(实现对图像的采集和压缩)-Using VHDL video control procedures (the achievement of the image acquisition and compression)
- 2022-12-07 16:40:03下载
- 积分：1
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Three-Pulse-VSR-
对三相电压型逆变器的数学模型进行了详细的数学推导，简单容易理解(Three-phase voltage inverter for the mathematical model of a detailed mathematical derivation is simple and easy to understand)
- 2011-08-14 22:30:28下载
- 积分：1
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PCIeData-Link-Layer-Specifications
PCIe数据链路层的协议详解，对做PCIe接口有非常重要的指导价值。(PCIe data link layer protocol detailed, do PCIe interface very important value.)
- 2012-08-31 12:33:15下载
- 积分：1
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eda技术与vhdl课件,很经典的学习课件
eda技术与vhdl课件,很经典的学习课件-VHDL EDA technology and courseware, it is a classic learning courseware
- 2022-05-18 23:44:31下载
- 积分：1
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7-segment
VHDL Design of BCD to 7-segment decoder
using PROM
- 2009-05-04 02:44:02下载
- 积分：1
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用Bresenham算法在FPGA上实现小数分频器，verilog编写，计算机图形法...
用Bresenham算法在FPGA上实现小数分频器，verilog编写，计算机图形法-Bresenham algorithm used in the FPGA to achieve a small number of crossovers, verilog preparation, computer graphics method
- 2022-03-11 03:26:38下载
- 积分：1
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用Verilog做的SD卡控制器(有详细的注释)
说明： SDIO 接口，实现SD卡的控制器功能，带有详细的注释(SDIO Interface,to realize the controller of SD Card,and have detail description.)
- 2020-06-16 22:00:01下载
- 积分：1
