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primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used stora...
本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
- 2022-07-07 05:54:22下载
- 积分：1
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ADC-Parameter
外部ADC采集数据，存为数组文件。通过程序读入，然后即可求出ADC的SNR、SINAD、THD、ENOB等。(External ADC data collection, stored as an array of documents. Read through the program, then the ADC SNR, SINAD, THD, ENOB can be calculated.)
- 2021-03-15 21:39:22下载
- 积分：1
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ARM-Verilog-HDL-IP-CORE
ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。(ARM processor IP core, written in verilog processor and CPU architecture knowledge.)
- 2020-09-21 10:27:52下载
- 积分：1
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adc_cfg
说明： adc器件ads62p49配置代码，已在工程中验证可用(Temperature sensor DS18B20 parses the code, has verified the ADC device configuration code, has been verified available)
- 2020-11-04 16:29:51下载
- 积分：1
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9850sin_function
ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)
- 2013-08-27 15:13:29下载
- 积分：1
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rdf0244-zc706-pcie-c-2015-4
利用FPGA开发板的PCIE接口实现数据的传输和发送。(Using the PCIE interface of FPGA development board to realize data transmission and transmission.)
- 2018-08-08 16:56:15下载
- 积分：1
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FIRfilterverilogHDL
FIR滤波器的verilog HDL代码示例，以16阶为例(Verilog HDL code for fir filter)
- 2015-07-08 17:05:38下载
- 积分：1
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weifen-program
基于FPGA微分程序代码及其电路驱动程序(Based on FPGA differential program
)
- 2011-12-19 12:17:59下载
- 积分：1
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详细介绍了VHDL的28个程序。从简单到复杂。介绍详细
详细介绍了VHDL的28个程序。从简单到复杂。介绍详细-Details of the 28 procedures VHDL. From simple to complex. Detailed introduction
- 2022-07-24 10:14:53下载
- 积分：1
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VHDL_count 从 0000 到 9999 7 段 LED 显示器 （đếm 慈 0000 đến 9999 hiển 施耐 4 领导 7 đoạn）
VHDL_count 从 0000 到 9999 7 段 LED 显示器 （đếm 慈 0000 đến 9999 hiển 施耐 4 领导 7 đoạn）
- 2022-02-24 20:50:42下载
- 积分：1
