登录
首页 » Verilog » CNA总线协议控制器Verilog

CNA总线协议控制器Verilog

于 2022-05-26 发布 文件大小:33.36 kB
0 56
下载积分: 2 下载次数: 1

代码说明:

This CAN Controller was tested with the Bosch VHDL Reference Model and passed all the tests. Because of the licensing issue it can not be published on the Opencores web site. The Can Controller was also implemented in real HW (12 boards were constantly talking to each other). The included test bench is not a real test bench and should be improved. However a volunteer is needed for such a job. I can provide some help but am not willing to write it by myself.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • abi123
    encoding and decoding of audio signal
    2013-02-02 18:59:16下载
    积分:1
  • DES
    说明:  自己写的DES的verilog实现。输入输出实现了并转串。(DES algorithm implemented in verilog.)
    2020-12-03 16:19:25下载
    积分:1
  • hamming_encodeadecode
    用Verilog语言编写的对m序列进行汉明码编译码的程序。具体实现为产生m序列后对其进行(7,4)汉明码编码并加错,然后将其纠错译码并输出,详细过程见仿真。(Written by Verilog m sequence of procedures for coding and decoding Hamming codes. Concrete realization of m sequence to produce its (7,4) hamming code and a mistake, and then error correction decoding and output, see the detailed process simulation.)
    2011-04-22 16:46:39下载
    积分:1
  • shift example
    shift example for verilog
    2018-12-18 05:24:04下载
    积分:1
  • 加法器
    说明:  4位加法器,4位数字相加及进位功能的实现,主要利用Verilog语言实现,简单轻松,且代码量少(a adder which can realize 4 bit numbers adding)
    2020-10-31 11:05:41下载
    积分:1
  • FPGA_电梯控制器
    本代码主要完成了一个以FPGA为平台的模拟电梯控制器。该设计以Xinlinx 公司Spartan3E  250  板为平台,结合了LCD1602外设和rs232串口发送外设,成功的实现了对一个三层楼的电梯实时运行状态的模拟,1602实时显示电梯及门的状态,并通过串口将当前楼层发送给电脑。代码语言为Verilog HDL.本设计使用的算法思想有三:1、将多个输入信号合并为一个信号。2、Moore 状态机的使用3、电梯多个状态的处理以及处理原则 共同学习,共同进步。
    2022-04-18 23:18:52下载
    积分:1
  • CH341-I2C-labview-all-vision
    CH341A的I2C接口Labview all vision (CH341A I2C Labview)
    2016-08-10 08:47:25下载
    积分:1
  • multifreqvhdl
    说明:  资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序,multifre1.vhd是倍频程序,multifre1.vwf是仿真波形文件,stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用,可以设置倍频数,修改实体参数N即可。(According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe that the procedure multiplier number, multifre1.vhd is the multiplier process, multifre1.vwf is the simulation waveform files, stp1.stp a virtual logic analyzer signaltap file. The multiplier process can be used directly, you can set the multiplier number, modify the parameter N can be solid.)
    2010-04-26 16:05:18下载
    积分:1
  • writereadflash
    这个是用VHDL实现FPGA对FLASH的读写。(This is achieved using VHDL FLASH FPGA to read and write.)
    2013-07-14 22:06:38下载
    积分:1
  • 32位-33M 从模式(target)PCI接口参考设计_lattice
    说明:  32位/33M 从模式(target)PCI接口参考设计,Lattice提供。由于PCI时序较复杂,此设计仅能供参考(32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only)
    2005-10-24 19:35:04下载
    积分:1
  • 696518资源总数
  • 104298会员总数
  • 46今日下载