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DDS波形发生器
DDS波形生成器verilog语言书写（FPGA型号cy4以上）(DDS generate verilog)
- 2017-07-17 22:25:11下载
- 积分：1
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64-bit-array-multiplier
说明： 这个是64bit矩阵乘法实现代码，语言是verilog。(This is the 64 bit matrix multiplication implementation code, and the language is Verilog.)
- 2020-06-18 13:22:03下载
- 积分：1
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encode
RS（255，223）编码器，已实际运用到产品中(RS (255,223) encoder has actually applied to products)
- 2021-05-13 00:30:02下载
- 积分：1
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qsys-niosii-triple-speed-ethernet-3c120-v10-1
qsys-niosii-triple-speed-ethernet-3c120-v10-1
- 2023-09-07 11:45:04下载
- 积分：1
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digital-design-and-synthesis
Verilog HDL 数字设计与综合，夏宇闻译。本书重点关注如何应用verilog语言进行数字电路和系统的设计和验证，不仅讲解语法，更从基本概念讲起，逐渐过渡到编程语言接口以及逻辑综合等高级主题。(The design and synthesis of Verilog HDL digital, Xia Wen translation. The book focused on how to apply the verilog language for the design and verification of digital circuits and systems, not only explain the grammar, the more I start from the basic concept, and a gradual transition to advanced topics such as programming language interface and logic synthesis.)
- 2012-10-23 00:16:59下载
- 积分：1
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myfir
verilog编写的16阶升余弦滤波器 采用直接型结构实现 对方波进行滤波 输出波形 含testbench文件(order raised cosine filter verilog written 16 direct-type structure to achieve the other wave filtering the output waveform containing testbench file)
- 2020-10-05 16:47:44下载
- 积分：1
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SAR-ADC
Complete Successive approximation Analog to digital converter along with the source code
- 2013-04-21 23:42:03下载
- 积分：1
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ISE为开发环境，Verilog语言编写程序
以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)
- 2020-06-20 00:00:02下载
- 积分：1
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processor
processor design istruction load pipeline ,hazard
- 2010-04-02 03:52:08下载
- 积分：1
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rscode
R S编 解 码 实 现 代 码
verilog语言(RS CODE AND ENCODE)
- 2013-05-19 16:19:55下载
- 积分：1
