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32FIRVHDL
基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器,运行速度更快,占用内存更小,延迟更小。
(32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.)
- 2014-05-12 21:11:19下载
- 积分:1
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Chapter10
第十章的代码。
本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench,所举实例具有很强的实用性和代表性,每个实例均给出了介绍、功能分析、程序代码和结果演示(Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate)
- 2009-11-17 13:52:32下载
- 积分:1
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gtwizard_254_127_ex_1113_3
说明: 配置GTH ip的例子工程,选用7 series 芯片的GTH 113quad的四个通道,在程序中每个链路利用自己的恢复时钟进行数据解码,所以四个通道可以各自独立运行;成功工作在2.54Gb/s的链路状态,长时间(>24小时)的测试,误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)
- 2019-06-17 21:33:56下载
- 积分:1
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8 位上下计数器
8位向上/向下计数器准备在FPGA上实现。我在一台Nexus4的Artix-7板进行了测试。它包含为了能够看到计数或上或下的转变的慢时钟。包括试验台
- 2022-01-25 23:47:51下载
- 积分:1
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基于fpga的三相spwm波的Verilog硬件实现
采用dds产生3路正弦波作为调制波,一路三角波形作为高频载波,按照spwm原理让正弦波和三角波送入比较器做比较判决运算。并且调制波和载波相位频率可调,外部按键调试即可。verilog实现,在altera的fpga芯片运行通过。
- 2022-02-20 22:39:06下载
- 积分:1
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rtcclock_latest.tar.gz
应用背景Project: A Wishbone Controlled Real--time Clock Core Purpose: Implement a real time clock, including alarm, count--down timer, stopwatch, variable time frequency, and more.关键技术基于FPGA的用verilog编写的时钟模块,具有时间计数,闹铃,以及计数器功能!具有很好的学习和使用价值。基于FPGA的用verilog编写的时钟模块,具有时间计数,闹铃,以及计数器功能!具有很好的学习和使用价值。
- 2022-01-24 16:17:40下载
- 积分:1
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fixpmul
verilog 有符号数 乘法器模块(verilog signed multiplyer)
- 2018-04-07 21:36:14下载
- 积分:1
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RTL_NAND_Flash_controller-master
RTL_NAND_Flash_controller-master,基础入门控制器,内存管理,fpga实现。miicron所属,
- 2022-04-12 05:21:10下载
- 积分:1
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fir48
48阶FIR设计,采用VHDL语言描述,门级映射……(48-oders FIR design with VHDL language and gate level)
- 2021-04-14 19:38:55下载
- 积分:1
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N-bits-by-M-bits
这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)
- 2013-10-05 19:44:52下载
- 积分:1