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rtcclock_latest.tar.gz

于 2022-01-24 发布 文件大小:208.52 kB
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应用背景Project: A Wishbone Controlled Real--time Clock Core Purpose: Implement a real time clock, including alarm, count--down timer, stopwatch, variable time frequency, and more.关键技术基于FPGA的用verilog编写的时钟模块,具有时间计数,闹铃,以及计数器功能!具有很好的学习和使用价值。基于FPGA的用verilog编写的时钟模块,具有时间计数,闹铃,以及计数器功能!具有很好的学习和使用价值。

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