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fpga_dk_ps2_vga
ps2 vga interface in vhdl code
- 2011-11-08 11:09:35下载
- 积分:1
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test_ad9852
使用FPGA来控制DDS信号的产生,从而达到高频信号产生的目的。使用的DDS芯片为AD9852,在QuartusII下编写。(Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.)
- 2010-01-27 17:02:16下载
- 积分:1
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xapp1026
XILINX中LWIP协议例子应用指南,有实际例子(Examples of applications in LWIP agreement XILINX Guide, a practical example)
- 2020-10-13 22:07:32下载
- 积分:1
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VHDL-TESTBENCH
VHDL TESTBENCH书写规范,对学习FPGA的同学很有帮助,掌握仿真语言书写规范。(VHDL TESTBENCH description of the norms, the students learn FPGA helpful, master the language of simulation techniques)
- 2016-12-15 21:33:24下载
- 积分:1
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weitongbu
基于fpga的位同步信号提取仿真 使用vhdl语言 quartus(To use vhdl language quartus fpga bit synchronization signal extraction-based simulation)
- 2020-12-29 17:29:00下载
- 积分:1
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counter
设计一个十进制计数器模块,输入端口包括 reset、up_enable 和 clk,输出端口为 count
和 bcd,当 reset 有效时(低电平),bcd 和 count 输出清零,当 up_enable 有效时(高电
平),计数模块开始计数(clk 脉冲数),bcd 为计数输出,当计数为 9 时,count 输出一
个脉冲(一个 clk周期的高电平,时间上与“bcd=9”时对齐)(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9" when aligned))
- 2013-04-13 19:53:29下载
- 积分:1
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LCD例程 altera官方Verilog代码 详尽简单实用
LCD例程 altera官方Verilog代码 详尽简单实用-LCD routines altera official Verilog code is simple and practical details
- 2022-09-20 01:40:03下载
- 积分:1
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DE2_Default
基于DE2开发板的VGA显示模块,仅供大家参考(DE2 development board based on the VGA display module, for your reference)
- 2008-07-21 16:12:32下载
- 积分:1
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Combined unit GPS clock synchronization detection unit merger GPS synchronized c...
合并单元内GPS同步时钟的检测
合并单元内GPS同步时钟的检测-Combined unit GPS clock synchronization detection unit merger GPS synchronized clock detection
- 2023-05-04 14:30:04下载
- 积分:1
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jisuanqishijianxianshi
基于FPGA编写一个时间显示,计数功能,年月显示的程序,(FPGA-based preparation of a time display, counting, years show program,)
- 2011-08-30 16:00:48下载
- 积分:1